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ADC-HZ12BMC Scheda tecnica(PDF) 2 Page - Murata Power Solutions Inc. |
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ADC-HZ12BMC Scheda tecnica(HTML) 2 Page - Murata Power Solutions Inc. |
2 / 6 page ABSOLUTE MAXIMUM RATINGS PARAMETERS LIMITS UNITS +15V Supply, Pin 28 +18 Volts –15V Supply, Pin 31 –18 Volts +5V Supply, Pin 16 +7 Volts Digital Inputs, Pins 14, 21 ±5.5 Volts Analog Inputs, Pins 24, 25 ±25 Volts Buffer Input, Pin 30 ±15 Volts Lead Temperature (10 seconds) 300 °C Functional Specifications (Typical at +25°C and ±15V and +5V supplies unless otherwise noted) INPUTS ADC-HX12B ADC-HZ12B Analog Input Ranges Unipolar 0 to +5V, 0 to +10V Bipolar ±2.5V, ±5V, ±10V Input Impedance 2.5k (0 to +5V, ±2.5V) 5k (0 to +10V, ±5V) 10k (±10V) Input Impedance with Buffer 50 megohms Input Bias Current of Buffer 125nA typical, 250nA max. Start Conversion +2V min. to +5.5V max. positive pulse with dur- ation of 100ns min. Rise and fall times <30ns. Logic "1" to "0" transition resets converter and initiates next conversion. Loading: 2 TTL loads. PERFORMANCE Resolution 12 bits Nonlinearity ±1/2LSB max. Differential Nonlinearity ±3/4LSB max. Accuracy Error Gain (before adjustment) ±0.2% Zero, Unipolar (before adj.) ±0.1% of FSR Offset, Bipolar (before adj.) ±0.2% of FSR Temperature Coefficient Gain ±20ppm/°C max. Zero, Unipolar ±5ppm/°C of FSR max. Offset, Bipolar ±10ppm/°C of FSR max. Diff. Nonlinearity Tempco ±2ppm/°C of FSR max. No Missing Codes Over opererating temperature range Conversion Time 12 Bits 20μs max. 8μs max. 10 Bits 15μs max. 6μs max. 8 Bits 10μs max. 4μs max. Buffer Settling Time (10V step) 3μs to ±0.01% Power Supply Rejection ±0.004%/% supply max. OUTPUTS Parallel Output Data 12 parallel lines of data held until next conversion command. VOUT ("0") +0.4V VOUT ("1") +2.4V Unipolar Coding Complementary binary Bipolar Coding Complementary offset binary Complementary two’s complement Serial Output Data NRZ successive decision pulses out, MSB first. Compl. binary or compl. offset binary coding. End of Conversion (Status) Conversion status signal. Output is logic "1" during reset and conversion and logic "0" when conversion complete. Clock Output Train of positive going +5V 100ns pulses. 600kHz for ADC-HX and 1.5MHz for ADC-HZ (pin 17 grounded). Internal Reference +6.3V Reference Tempco ±20ppm/°C max. External Reference Current 2.5mA max. POWER REQUIREMENTS Power Supply Voltages +15V ±0.5V at +20mA –15V ±0.5V at –25mA +5V ±0.25V at +85mA PHYSICAL/ENVIRONMENTAL Operating Temp. Range, Case 0 to +70°C or –55 to +125°C Storage Temperature Range –65 to +150°C Package Type 32-pin ceramic TDIP Weight 0.5 ounces (14 grams) Thermal Impedance JC 6°C/W JA 30°C/W Footnotes: Adjustable to zero. FSR is full scale range and is 10V for 0 to +10V or ±5V inputs and 20V for ±10V input, etc. Without buffer amplifier used. ADC-HZ may require external adjustment of clock rate. Short cycled operation. All digital outputs can drive 2 TTL loads. TECHNICAL NOTES 1. It is recommended that the ±15V power input pins both be bypassed to ground with a 0.01μF ceramic capacitor in parallel with a 1μF electrolytic capacitor and the +5V power input pin be bypassed to ground with a 10μF electrolytic capacitor as shown in the connection diagrams. In addition, GAIN ADJUST (pin 27) should be bypassed to ground with a 0.01μF ceramic capacitor. These precautions will assure noise free operation of the converter. 2. DIGITAL COMMON (pin 15) and ANALOG COMMON (pin 26) are not connected together internally, and therefore must be connected as directly as possible externally. It is recommended that a ground plane be run underneath the case between the two commons. Analog ground and ±15V power ground should be run to pin 26 whereas digital ground and +5V ground should be run to pin 15. 3. External adjustment of zero or offset and gain are made by using trimming potentiometers connected as shown in the connection diagrams. The potentiometer values can be between 10k and 100k Ohms and should be 100ppm/°C cermet types. The trimming pots should be located as close as possible to the con- verter to avoid noise pickup. In some cases, for example 8-bit short-cycled operation, external adjustment may not be necessary. 4. Short-cycled operation results in shorter conversion times when the conversion is truncated to less than 12 bits. This is done by connecting SHORT CYCLE (pin 14) to the output bit following the last bit desired. For example, for an 8-bit conversion, pin 14 is connected to the bit 9 output. Maximum conversion times are given for short-cycled conversions of 8 or 10 bits. In these two cases, the clock rate is accelerated by connecting the CLOCK RATE adjust (pin 17) to +5V (10 bits) or +15V (8 bits). The clock rate should not be arbitrarily speeded up to exceed the maximum conversion rate at a given resolution, as missing codes will result. 5. Note that output coding is complementary coding. For unipolar operation it is complementary binary, and for bipolar operation it is complementary offset binary or complementary two’s complement. In cases in which bipolar coding of offset binary or two’s complement is required, this can be achieved by inverting the analog input to the converter (using an op amp connected for gain of –1). The converter is then calibrated so that –FS analog input gives an output code of 0000 0000 0000, and +FS – 1LSB gives 1111 1111 1111. 6. These converters can be operated with an external clock. To accomplish this, a negative pulse train is applied to START CONVERT (pin 21). The rate of the external clock must be lower than the rate of the internal clock as adjusted (see Short Cycle Operation tables) for the converter resolution selected. The pulse width of the external clock should be between 100 and 300 nanoseconds. Each N-bit conversion cycle requires a pulse train of N + 1 clock pulses for completion, e.g., an 8-bit conversion requires 9 clock pulses for completion. A continuous pulse train may be used for consecutive conversions, resulting in an N-bit conversion every N + 1 pulses, or the E.O.C. output may be used to gate a continuous pulse train for single conversions. 7. When the input buffer amplifier is used, a delay equal to its settling time must be allowed between the input level change, such as a multiplexer channel change, and the negative-going edge of the START CONVERT pulse. If the buffer is not required, BUFFER INPUT (pin 30) should be tied to ANALOG COMMON (pin 26). This prevents the unused amplifier from introducing noise into the converter. For applications not using the buffer, the converter must be driven from a source with an extremely low output impedance. ADC-HX, ADC-HZ Series 12-Bit, 8 and 20μsec Analog-to-Digital Converters Technical enquiries email: sales@murata-ps.com, tel: +1 508 339 3000 www.murata-ps.com MDA_ADCHXHZ.B01 Page 2 of 6 |
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