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MC-ACT-UARTF Scheda tecnica(PDF) 5 Page - Actel Corporation

Il numero della parte MC-ACT-UARTF
Spiegazioni elettronici  FastUART
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Produttore elettronici  ACTEL [Actel Corporation]
Homepage  http://www.actel.com
Logo ACTEL - Actel Corporation

MC-ACT-UARTF Scheda tecnica(HTML) 5 Page - Actel Corporation

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Fast UART
Memec Design
February 25, 2003
5
Optimized for
Signal Descriptions
The following signal descriptions define the IO signals.
Signal
Direction Description
clk
in
System clock, rising edge used only, must be at least 64 times higher than
maximum baudrate
reset_n
in
Asynchronous system reset, active low, goes to all flip flops
fuart_config.baudrate[15:0]
in
Baudrate configuration value
fuart_config.data_78
in
Transmit and receive data size:
‘0’: use 7 bit data
‘1’: use 8 bit data
fuart_config.par_ebl
in
Parity enable:
‘0’: no parity check, no parity bit transmitted and received
‘1’: use parity check, parity bit inserted and checked
fuart_config.par_pol
in
Parity polarity:
‘0’: use even parity
2
‘1’: use odd parity
This parameter is ignored when par_ebl is inactive!
fuart_config.stop_12
in
Transmit and receive stop bit number:
‘0’: use and check 1 stop bit
‘1’: use and check 2 stop bits
fuart_config.tx_run
in
Transmit control:
‘0’: transmitter off, ignores all inputs, outputs inactive
‘1’: transmitter is working
fuart_config.rx_run
in
Receive control:
‘0’: receiver off, ignores all inputs, outputs are inactive
‘1’: receiver is working
rx_pin
in
Pin for the incoming bit stream. The inactive state is logic ‘1’
tx_pin
out
Pin for the outgoing bit stream. The inactive state is logic ‘1’
fuart_tx_data[7:0]
in
8bit data to be transmitted. For 7bit configuration, bit[7] is ignored.
Data must be valid and stable when fuart_tx_we is active.
fuart_tx_we
in
Event for storing the tx_data in the transmit shift register and start of
transmission. It’s up to the system to not activate this input when the MC-ACT-
UARTF is busy.
fuart_tx_busy
out
When the transmitter is sending a byte, this status output remains active (logic
‘1’) until it is ready to send a new byte. While fuart_tx_busy is ‘1’, fuart_tx_we
mustn’t be activated.
fuart_rx_data[7:0]
out
8bit data that has been received. For 7bit configuration, bit[7] is ignored. The
data will be stable only during the active phase of fuart_rx_ready. Add a buffer
register if data should remain stable until reception of next character.
fuart_rx_ready
out
Event (active ‘1’) for signalling, that a new byte has arrived and the
fuart_rx_data is valid now.
fuart_par_error
out
Event (active ‘1’) for signalling, that a byte with wrong parity has been received
and aborted (it’s not visible at rx_ready)
This signal is always inactive when par_ebl is deactivated.
fuart_form_error
out
Event (active ‘1’) for signalling, that a byte with wrong format has been
received and aborted (it’s not visible at rx_ready)
Table 2: Core I/O Signals
2 number of ones in a byte, including parity bit is even


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