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MC-ACT-VME32-VHD Scheda tecnica(PDF) 4 Page - Actel Corporation

Il numero della parte MC-ACT-VME32-VHD
Spiegazioni elettronici  Flexible slave VME controller Full interrupt controller (ROAK)
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Produttore elettronici  ACTEL [Actel Corporation]
Homepage  http://www.actel.com
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MC-ACT-VME32-VHD Scheda tecnica(HTML) 4 Page - Actel Corporation

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Signal
Direction
Description
VME_DS1_N
Input
VME Data Strobe 1: Active low signal used for the selected location part of the data.
VME_WRITE_N
Input
VME Read/Write: Active low signal which is used by the master to indicate the data direction.
VME_BERR_N
Input
VME Bus Error: Active low signal driven by other modules indicating that the data transfer was unsuccessful.
VME_IACK_N
Input
VME Interrupt Acknowledge: When driven low, the VME_IACKIN_N causes the IACK daisy-chain driver,
located in slot 1, to propagate a falling edge down the interrupt acknowledge daisy-chain.
VME_IACKIN_N
Input
VME Interrupt Acknowledge Input Daisy-Chain: This active low signal is used as input of the module for the
daisy-chain interrupt acknowledge.
VME_IACKOUT_N
Output
VME Interrupt Acknowledge Output Daisy-Chain: This active low signal is used as output of the module for
the daisy-chain interrupt acknowledge.
VME_IRQ_N[6:0]
Output
VME Interrupt Request Lines: Interrupters request interrupts by driving an interrupt request line low.
VME_IRQ_N[7] has the highest priority. These signals have to be connected to open collector drivers.
INT_USER_ADDR[31:1]
Output
Registered VME Address Bus: Synchronized on the falling edge of VME_AS_N. This bus is used to decode
the address and to active an access signal on the user part.
INT_USER_AM[5:0]
Output
Registered VME Address Modifier Bus: Synchronized on the falling edge of VME_AS_N. This bus is used
to decode the address modifier and to active an access signal on the user part.
USER_ACCESS
Input
User Access Signal: The user has 50 ns time to decode the address and asserting the USER_ACCESS
signal when addressed.
USER_ACC_REQ
Output
User Access Request: Active high signal which requests for an access on the VME bus. Valid until USER_
ACC_RDY acknowledges the request (or VME bus error occurs).
USER_ACC_RDY
Input
User Side Acknowledgement Signal: Acknowledge the request of the access on the VME bus of the user
part.
USER_ADDR[31:1]
Output
User Address: Address used for the access on the user part.
USER_AM[5:0]
Output
User Address Modifier: Address modifier used for the access on the user part.
USER_WR_DATA[31:0]
Output
User Write Data: The data[31:24] are valid while USER_BE4 is high, data[23:16] while USER_BE3,
data[15:8] while USER_BE2 and data[7:0] while USER_BE1.
USER_RD_DATA[31:0]
Input
User Read Data: The read data has to be valid when USER_ACC_RDY is high.
USER_RW_N
Output
User Read/Write Signal: A low signal indicates that the data are written in the user part and a low signal, that
the data are read.
USER_BE1
Output
User Byte 1 Enable: Active high signal enabling the low byte [7:0] of the data.
USER_BE2
Output
User Byte 2 Enable: Active high signal enabling the high byte [15:8] of the data.
USER_BE3
Output
User Byte 3 Enable: Active high signal enabling the high byte [23:16] of the data.
USER_BE4
Output
User Byte 4 Enable: Active high signal enabling the high byte [31:24] of the data.
USER_IREQ
Input
User Interrupt request: This active high signal indicates that an interrupt is pending on a VME interrupt will
be generated. It will return to zero with USER_IACK active.
USER_IACK
Output
User Interrupt Acknowledge: An active one event which indicates the end of a valid interrupt acknowledge
cycle.
USER_ILEV[2:0]
Input
User Interrupt Level: This bus indicates the level of priority of the pending interrupt. It will generate the
corresponding VME_IRQ.
USER_IVEC[31:0]
Input
User Interrupt Vector: The interrupt vector will be transmitted on the VME data bus during the
acknowledgement of the interrupt.
Table 2: VME Core Signal List


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