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AD1882AJCPZ-RL Scheda tecnica(PDF) 6 Page - Analog Devices |
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AD1882AJCPZ-RL Scheda tecnica(HTML) 6 Page - Analog Devices |
6 / 20 page Rev. 0 | Page 6 of 20 | August 2008 AD1882A HD AUDIO LINK SPECIFICATIONS HD Audio signals comply with the High Definition Audio spec- ifications. Please refer to these specifications at: http://www.intel.com/standards/hdaudio/ POWER-DOWN STATES DM_DATA Input Signal High (VIH)DVGPIO × 0.60 DVGPIO V Input Signal Low (VIL)0 DVGPIO × 0.24 V Input Leakage Current (Signal High) (IIH) –150 nA Input Leakage Current (Signal Low) (IIL)–50 nA S/PDIF_OUT Output Signal High (VOH)IOUT = –500 μADVGPIO × 0.72 DVGPIO V Output Signal Low (VOL)IOUT = +1500 μA0 DVGPIO × 0.10 V POWER SUPPLY Analog (AV DD) 3.3 V ± 5% Power Supply Range Power Dissipation Supply Current 3.13 3.30 116 35 3.46 V mW mA Digital (DVDD) 3.3 V ± 10% Power Supply Range Power Dissipation Supply Current 2.97 3.30 162 49 3.63 V mW mA Digital I/O (DVIO) 3.3 V ± 10% Power Supply Range Power Dissipation Supply Current 2.97 3.30 3.96 1.20 3.63 V mW mA Digital I/O (DVIO) 1.5 V ± 5.5% Power Supply Range Power Dissipation Supply Current 2.97 3.30 3.96 1.20 3.63 V mW mA Digital GPIO (DVGPIO) 3.3 V ± 10% Power Supply Range Power Dissipation Supply Current 2.97 3.30 3.63 1.10 3.63 V mW mA Power Supply Rejection (100 mV p-p Signal @ 1 kHz) 1 80 dB 1 Guaranteed but not tested. 2 Measurements reflect main ADC. 3 RMS values assume sine wave input. Parameter Min Typ Max Unit Table 5. Power-Down States Parameter IDVDD Typ IAVDD Typ Unit Function Node In D0, All Nodes Active 49 35 mA Function Node in D3 16 0.7 mA Codec in RESET 33mA Individual Block Power Savings DAC Pair Powered Down Saves (Each) ADC Pair Powered Down Saves (Each) Mixer Power Control (and Associated Amps) Saves MIC_BIAS Powered Down Saves1 1 Powering down the MIC_BIAS powers down all port MIC_BIAS pins. This disables all microphone bias circuits, setting them to the high-Z state. 6 5 0 0 6 4.4 3 1.0 mA mA mA mA |
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