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TDA1180 Scheda tecnica(PDF) 8 Page - STMicroelectronics |
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TDA1180 Scheda tecnica(HTML) 8 Page - STMicroelectronics |
8 / 12 page APPLICATION INFORMATION Pin 1 - Positive supply The operating supply voltage of the device ranges from 10V to 13.2V Pin 2 and 3 - Output The outputs of TDA1180P are suitable for driving transistor output stages, they deliver positive pulse at Pin 3 and negative pulse at Pin 2. The negative pulse is used for direct driving of the output stage, while positive pulse is useful when a driver stage is required. The rise and fall times of the output pulses are about 150 ns so that interference due to radiation are avoided. Furthermore the output stages are internally pro- tected against short circuit. Pin 4 - Protection circuit input By connecting Pin 4 of the IC to earth the output pulses at Pin 2 and 3 are shut off ; this function has been introduced to produced to protect the final stages from overloads. The same pulses are also shut off when the supply voltage falls below 4V. Pin 5 - Phase shifter filter To compensate for the delay introduced by the line final stages, the flyback pulses to Pin 6 and the oscillator waveform are compared in the oscillator- flyback pulse phase comparator. The result of the comparison is a control current which, after it has been filtered by the external capacitor connected to Pin 5, is sent to a phase shifter which adequately regulates the phase of the output pulses. The maximum phase shift allowed is: td = tp - tf where tf is the flyback pulse duration. Pin 5 has high input and output resistance (current generator). Pin 6 - Flyback input The flyback pulse drives the high impedance input through a resistor in order to limit the input current to suitable maximum values. The flyback input pulses are processed by a double threshold circuit; this generates the blanking pulses by sensing low level flyback voltage and the pulses to drive the phase comparator by sensing high level flyback voltage, therefore phase jitter caused by ringing normally associated with the flyback pulse, is avoided. Pin 7 - Key and blanking pulse output The key pulse for taking out the burst from the chrominance signal is generated from the oscillator ramp and has therefore a fixed phase position with respect to the sync. The key pulse is then added internally to the blank- ing pulse obtained by correctly forming the flyback pulse present at Pin 6. The sum of the two signals (sandcastle pulse) is available on low impedance at output Pin 7. Pin 8 and 9 - Sync separators inputs The video signal is applied by means of two distinct biasing networks to pins 8 and 9 of the IC and therefore to the respective vertical and horizontal sync separators. The latter take the sync pulses out of the video signal and make them available to the rest of the circuit for further processing. f (kHz) O ϕ 1 0 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 (µs) Figure 4 : Loop Gain f (kHz) O V (V) S 16 15 15.5 15.625 0 2 4 6 8 10 12 14 16 Figure 3 : Free Running Frequency versus Supply Voltage TDA1180P 8/12 |
Codice articolo simile - TDA1180 |
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Descrizione simile - TDA1180 |
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