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FDG6322C Scheda tecnica(PDF) 3 Page - Fairchild Semiconductor

Il numero della parte FDG6322C
Spiegazioni elettronici  Dual N & P Channel Digital FET
Download  9 Pages
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Produttore elettronici  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FDG6322C Scheda tecnica(HTML) 3 Page - Fairchild Semiconductor

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Electrical Characteristics (continued)
SWITCHING CHARACTERISTICS (Note 2)
Symbol
Parameter
Conditions
Type
Min
Typ
Max
Units
t
D(on)
Turn - On Delay Time
N-Channel
N-Ch
5
10
nS
V
DD = 5 V, ID = 0.5 A,
P-Ch
7
15
t
r
Turn - On Rise Time
V
GS = 4.5 V, RGEN = 50
N-Ch
4.5
10
nS
P-Ch
8
16
t
D(off)
Turn - Off Delay Time
P-Channel
N-Ch
4
8
nS
V
DD = -5 V, ID = -0.5 A,
P-Ch
55
80
t
f
Turn - Off Fall Time
V
GS = -4.5 V, RGEN = 50
N-Ch
3.2
7
nS
P-Ch
35
60
Q
g
Total Gate Charge
N-Channel
N-Ch
0.29
0.4
nC
V
DS= 5 V, ID = 0.22 A,
P-Ch
1.1
1.5
Q
gs
Gate-Source Charge
V
GS = 4.5 V
N-Ch
0.12
nC
P- Channel
P-Ch
0.31
Q
gd
Gate-Drain Charge
V
DS = -5 V, ID = -0.41 A,
N-Ch
0.03
nC
V
GS = -4.5 V
P-Ch
0.29
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
Maximum Continuous Drain-Source Diode Forward Current
N-Ch
0.25
A
P-Ch
-0.25
V
SD
Drain-Source Diode Forward Voltage
V
GS = 0 V, IS = 0.5 A
(Note 2)
N-Ch
0.8
1.2
V
V
GS = 0 V, IS = -0.5 A
(Note 2)
P-Ch
-0.85
-1.2
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed
by design while RθCA is determined by the user's board design. RθJA = 415
OC/W on minimum mounting pad on FR-4 board in still air.
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
FDG6322C Rev.F1


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