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DAC9881SBRGER Scheda tecnica(PDF) 9 Page - Texas Instruments |
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DAC9881SBRGER Scheda tecnica(HTML) 9 Page - Texas Instruments |
9 / 38 page TIMING CHARACTERISTICS for Figure 1 (1) (2) (3) DAC9881 www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008 At –40°C to +105°C, unless otherwise noted. PARAMETER CONDITIONS MIN MAX UNIT 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 40 MHz fSCLK Maximum clock frequency 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 50 MHz 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 50 ns t1 Minumum CS high time 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 30 ns 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 10 ns Delay from CS falling edge to SCLK rising t2 edge 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 8 ns 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 0 ns Delay from SCLK falling edge to CS falling t3 edge 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 0 ns 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 10 ns t4 SCLK low time 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 10 ns 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 15 ns t5 SCLK high time 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 10 ns 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 25 ns t6 SCLK cycle time 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 20 ns 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 10 ns Delay from SCLK rising edge to CS rising t7 edge 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 10 ns 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 8 ns t8 Input data setup time 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 5 ns 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 5 ns t9 Input data hold time 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 5 ns 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 10 ns Delay from CS rising edge to LDAC falling t14 edge 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 5 ns 2.7 ≤ AVDD < 3.6V, 2.7 ≤ IOVDD ≤ AVDD 15 ns t15 LDAC pulse width 3.6 ≤ AVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ AVDD 10 ns (1) All input signals are specified with tR = tF = 2ns (10% to 90% of IOVDD) and timed from a voltage level of IOVDD/2. (2) Ensured by design. Not production tested. (3) Sample tested during the initial release and after any redesign or process changes that may affect these parameters. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): DAC9881 |
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