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LC4128ZE5MN144IES Scheda tecnica(PDF) 4 Page - Lattice Semiconductor |
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LC4128ZE5MN144IES Scheda tecnica(HTML) 4 Page - Lattice Semiconductor |
4 / 54 page Lattice Semiconductor ispMACH 4000ZE Family Data Sheet 4 Figure 3. AND Array Enhanced Logic Allocator Within the logic allocator, product terms are allocated to macrocells in product term clusters. Each product term cluster is associated with a macrocell. The cluster size for the ispMACH 4000ZE family is 4+1 (total 5) product terms. The software automatically considers the availability and distribution of product term clusters as it fits the functions within a GLB. The logic allocator is designed to provide two speed paths: 20-PT Speed Locking path and an up to 80-PT path. The availability of these two paths lets designers trade timing variability for increased perfor- mance. The enhanced Logic Allocator of the ispMACH 4000ZE family consists of the following blocks: • Product Term Allocator • Cluster Allocator • Wide Steering Logic Figure 4 shows a macrocell slice of the Logic Allocator. There are 16 such slices in the GLB. Figure 4. Macrocell Slice PT0 PT1 Cluster 0 PT2 PT3 PT4 In[0] In[34] In[35] Note: Indicates programmable fuse. PT80 PT81 PT82 Shared PT Clock Shared PT Initialization Shared PTOE/BIE PT76 PT77 PT78 PT79 PT75 Cluster 15 to n+1 to n-1 to n-2 from n-1 from n-4 from n+2 from n+1 5-PT From n-4 1-80 PTs To n+4 To XOR (MC) Cluster Individual Product Term Allocator Cluster Allocator SuperWIDE™ Steering Logic n |
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