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LAXP2-17E-5TN114E Scheda tecnica(PDF) 11 Page - Lattice Semiconductor

Il numero della parte LAXP2-17E-5TN114E
Spiegazioni elettronici  LA-LatticeXP2 Family Data Sheet
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Produttore elettronici  LATTICE [Lattice Semiconductor]
Homepage  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

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2-8
Architecture
Lattice Semiconductor
LA-LatticeXP2 Family Data Sheet
Figure 2-5. Clock Divider Connections
Clock Distribution Network
LA-LatticeXP2 devices have eight quadrant-based primary clocks and between six and eight flexible region-based
secondary clocks/control signals. Two high performance edge clocks are available on each edge of the device to
support high speed interfaces. The clock inputs are selected from external I/Os, the sysCLOCK PLLs, or routing.
Clock inputs are fed throughout the chip via the primary, secondary and edge clock networks.
Primary Clock Sources
LA-LatticeXP2 devices derive primary clocks from four sources: PLL outputs, CLKDIV outputs, dedicated clock
inputs and routing. LA-LatticeXP2 devices have two to four sysCLOCK PLLs, located in the four corners of the
device. There are eight dedicated clock inputs, two on each side of the device. Figure 2-6 shows the primary clock
sources.
RST
RELEASE
÷1
÷2
÷4
÷8
CLKOP (GPLL)
ECLK
CLKDIV


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