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STP10NC50 Scheda tecnica(PDF) 1 Page - STMicroelectronics |
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STP10NC50 Scheda tecnica(HTML) 1 Page - STMicroelectronics |
1 / 7 page STP10NC50 STP10NC50FP N - CHANNEL 500V - 0.48 Ω - 10A - TO-220/TO-220FP PowerMESH ™ MOSFET PRELIMINARY DATA s TYPICAL RDS(on) = 0.48 Ω s EXTREMELY HIGH dv/dt CAPABILITY s 100% AVALANCHE TESTED s VERY LOW INTRINSIC CAPACITANCES s GATE CHARGE MINIMIZED DESCRIPTION Using the latest high voltage MESH OVERLAY ™ process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charge and switching characteristics. APPLICATIONS s HIGH CURRENT, HIGH SPEED SWITCHING s SWITCH MODE POWER SUPPLIES (SMPS) s DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVE ® INTERNAL SCHEMATIC DIAGRAM November 1999 1 2 3 TYPE VDSS RDS(on) ID ST P10NC50 ST P10NC50FP 500 V 500 V <0. 52 Ω <0. 52 Ω 10 A 10 A ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Un it ST P10NC50 STP10NC50F P VDS Drain-source Volt age (VGS =0) 500 V VDGR Drain- gate Voltage (RGS =20 k Ω) 500 V VGS Gate-source Voltage ± 30 V ID Drain Current (continuous) at Tc =25 oC 10 10(*) A ID Drain Current (continuous) at Tc = 100 oC6.3 6.3(*) A IDM ( •) Drain Current (pulsed) 40 40 A Ptot T otal Dissipation at Tc =25 oC 135 40 W Derat ing Factor 1.08 0.32 W / o C dv/dt (1) Peak Diode Recovery voltage slope 3 3 V/ns VISO Insulat ion Withstand Voltage (DC) 2000 V Tstg Storage Temperat ure -65 to 150 o C Tj Max. Operat ing Junction T emperature 150 o C ( •) Pulse width limited by safe operating area ( 1)ISD ≤ 10 A, di/dt ≤100 A/µs, VDD ≤ V(BR)DSS,Tj ≤ TJMAX (*) Limited only by maximum temperature allowed TO-220 TO-220FP 1 2 3 1/7 |
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