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STULPI01BTBR Scheda tecnica(PDF) 8 Page - STMicroelectronics |
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STULPI01BTBR Scheda tecnica(HTML) 8 Page - STMicroelectronics |
8 / 44 page Bump configuration STULPI01A - STULPI01B 8/44 Bump Symbol Type Description F2 NC Not connected. E2 VB_REF_FAULT I Voltage reference for internal OC detector input or digital input from external OC detector (V3V3V referred). 5V tolerant. D4 PSWn O External charge pump control, active low. 5V tolerant, open drain. F5 XI I External clock input (1V8VIO referred). Crystal terminal (on request). F6 XO O Left floating or connect to GND when external clock signal is used. Crystal terminal on request. F3 VBAT PWR Battery power input for the LDO (3 V – 4.5 V). Bypass VBAT to GND with a 1µF capacitor. E3 3V3V PWR 3.3V LDO output. Bypass 3V3V to GND with a 1.5µF capacitor. E6 1V2V PWR 1.2V LDO output. Bypass 1V2V to GND with a 1.5µF capacitor. C2 RREF I/O Reference resistor (12k Ω ±1%). B2/B3/B5 1V8VIO PWR Digital I/O supply voltage 1.8V. Bypass each 1V8VIO to GND with a 100nF-1uF capacitor. Balls B2-B5 can share common capacitor. C5/D2 GND PWR Ground. B4/E4/E1 GND PWR Ground. Table 2. Pinout and bump description (continued) |
Codice articolo simile - STULPI01BTBR |
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Descrizione simile - STULPI01BTBR |
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