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ST95020WM6TR Scheda tecnica(PDF) 9 Page - STMicroelectronics |
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ST95020WM6TR Scheda tecnica(HTML) 9 Page - STMicroelectronics |
9 / 18 page Byte Write Operation Prior to any write attempt, the write enable latch must be set by issuing the WREN instruction. First the device is selected (S = low) and a serial WREN instruction byte is issued. Then the product is de- selected by taking S high. After the WREN instruc- tion byte is sent, the Memory will set the write enable latch and then remain in standby until it is deselected. Then the write state is entered by selecting the chip, issuing two bytes of instruction and address, and one byte of data. Chip Select (S) must remain low for the entire duration of the operation. The product must be deselectedjust after the eighth bit of data has been latched in. If not, the write process is cancelled. As soon as the product is deselected, the self-timed write cycle is initiated. While the write isin progress, the status register may be read to check BP1, BP0, WEL and WIP. WIP is high during the self-timed write cycle. When the cycle is completed, the write enable latch is reset. Page Write Operation A maximum of 16 bytes of data may be written during one non-volatile write cycle. All 16 bytes must reside on the same page. The page write mode is the same as the byte write mode except that instead of deselecting the device after the first byte of data, up to 15 additionalbytes can be shifted in prior to deselecting the chip. A page address begins with address xxxx 0000 and ends with xxxx 1111. If the address counter reaches xxxx 1111and the clock continues, the counter will roll over to the first address of the page (xxxx 0000) and overwrite any previously written data. The programming cy- cle will only start if the S transition occurs just after the eighth bit of data of a word is received. POWER ON STATE After a Power up the Memory is in the following state: – The device is in the low power standby state. – The chip is deselected. – The chip is not in hold condition. – The write enable latch is reset. – BP1 and BP0 are unchanged (non-volatile bits). C D AI01445 S Q 2 1 3 4 5 6 7 8 9 10 111213 1415 HIGH IMPEDANCE INSTRUCTION STATUS REG. 0 Figure 11. WRSR: Write Status Register Sequence 9/18 ST95040, ST95020, ST95010 |
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