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ST93C56M1013TR Scheda tecnica(PDF) 9 Page - STMicroelectronics |
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ST93C56M1013TR Scheda tecnica(HTML) 9 Page - STMicroelectronics |
9 / 13 page Erase All The Erase All instruction (ERAL) erases the whole memory (all memory bits are set to ’1’). A dummy address is input during the instruction transfer and the erase is made in the same way as the ERASE instruction. If the ST93C56 is still performing the erase cycle, the Busy signal (Q = 0) will be returned if S is driven high, and the ST93C56 will ignore any data on the bus. When the erase cycle is com- pleted, the Ready signal (Q = 1) will indicate (if S is driven high) that the ST93C56 is ready to receive a new instruction. Write All The Write All instruction (WRAL) writes the Data Input byte or word to all the addresses of the memory. If the ST93C56 is still performing the write cycle, the Busy signal (Q = 0) will be returned if S is driven high, and the ST93C56 will ignore any data on the bus. When the write cycle is completed, the Ready signal (Q = 1) will indicate (if S is driven high) that the ST93C56 is ready to receive a new instruction. READY/BUSY Status During every programming cycle (after a WRITE, ERASE, WRAL or ERAL instruction) the Data Out- put (Q) indicates the Ready/Busy status of the memory when the Chip Select (S) is driven High. Once the ST93C56 is Ready, the Ready/Busy status is available on the Data Output (Q) until a new start bit is decoded or the Chip Select (S) is brought Low. COMMON I/O OPERATION The Data Output (Q) and Data Input (D) signals can be connected together, through a current limiting resistor, to form a common, one wire data bus. Some precautions must be taken when operating the memory with this connection, mostly to prevent a short circuit between the last entered address bit (A0) and the first data bit output by Q. The reader may also refer to the SGS-THOMSON application note ”MICROWIRE EEPROM Common I/O Opera- tion”. DIFF ERENCES BETWEEN ST93C56 AND ST93C56C The ST93C56C is an enhanced version of the ST93C56 and offers a functional security filtering glitches on the clock input (C). The following description will detail the Clock pulse counter (available only on the ST93C56C). In a normal environment, the ST93C56 expects to receive the exact amount of data on the D input, that is, the exact amount of clock pulses on the C input. In a noisy environment, the number of pulses re- ceived (on the clock input C) may be greater than the clock pulsesdelivered by the Master (Microcon- troller) driving the ST93C56C. In such a case, a part of the instruction is delayed by one bit (see Figure 9), and it may induce an erroneous write of data at a wrong address. The ST93C56C has an on-chip counter which counts the clock pulses from the Start bit until the falling edge of the Chip Select signal. For the WRITE instructions, the number of clock pulses incoming to the counter must be exactly 20 (with the Organisation by 8) from the Start bit to the falling edge of Chip Select signal (1 Start bit + 2 bits of Op-code + 9 bits of Address + 8 bits of Data = 20): if so, the ST93C56C executes the WRITE instruction; if the number of clock pulses is not equal to 20, the instruction will not be executed (and data will not be corrupted). In the same way, when the Organisation by 16 is selected, the number of clock pulses incoming to the counter must be exactly 27 (1 Start bit + 2 bits of Op-code + 8 bits of Address + 16 bits of Data = 27) from the Start bit to the falling edge of Chip Select signal: if so, the ST93C56C executes the WRITE instruction; if the number of clock pulses is not equal to 27, the instruction will not be executed (and data will not be corrupted). The clock pulse counter is active only on ERASE and WRITE in- structions (WRITE, ERASE, ERAL, WRALL). 9/13 ST93C56/56C, ST93C57C |
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