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ST1284-02A8RL Scheda tecnica(PDF) 5 Page - STMicroelectronics |
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ST1284-02A8RL Scheda tecnica(HTML) 5 Page - STMicroelectronics |
5 / 7 page 5/7 ST1284-xxA8/T8 To have a good approximation of the remaining voltages at both Vin and Vout stages, we give the typical dynamical resistance value Rd. By taking into account these following hypothesis : Rt>Rd, Rg>Rd and Rload>Rd, it gives these formulas: Vinput RV RV R gBR d PP g = + .. Voutput R V R Vinput R tBR d t = + .. The results of the calculation done for VPP=8kV, Rg=330 Ω (IEC61000-4-2 standard), VBR=7V (typ.) and Rd = 1 Ω (typ.) give: Vinput = 31.2 V Voutput = 7.95 V This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this approximation the parasitic inductance effect was not taken into account. This could be few tenths of volts during few ns at the input side. This parasitic effect is not present at the output side due the low current involved after the resistance R. The measurements done here after show very clearly (Fig. A5) the high efficiency of the ESD protection : - no influence of the parasitic inductances on Vout stage - Voutput clamping voltage very close to VBR (positive strike) and -VF (negative strike) ST1284 Vinput Voutput ESD SURGE Fig. A4: Measurement conditions Fig. A5: Remaining voltage at the input and output of the device during a ±16kV ESD surge (IEC61000-4-2). |
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