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ST10R272L-B0 Scheda tecnica(PDF) 4 Page - STMicroelectronics

Il numero della parte ST10R272L-B0
Spiegazioni elettronici  16-BIT ROMLESS LOW VOLTAGE MCU WITH MAC
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Produttore elettronici  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10R272L-B0 Scheda tecnica(HTML) 4 Page - STMicroelectronics

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ST10R272L-B0 Errata Sheet
4/4
3 HISTORY OF FIXED FUNCTIONAL PROBLEMS OF THE ST10R272L:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics
products are not authorized for use as critical components in life support devices or systems without the express written approval of
STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
©2000 STMicroelectronics - All Rights Reserved.
Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
STMicroelectronics Group of Companies
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain
Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
Functional
Problem
Short Description
fixed
in
Step
CPU.17
Arithmetic Overflow by DIVLU instruction
B0
TRAP_B.1
ATOMIC / EXTended sequences in Class B Hardware Trap
B0
Kfm_BR03
Pipeline conflict after CoStore operation
B0
Kfm_BR04
Wrong PSW value after byte instruction
B0
Kfm_BR05
Wrong result for BFLDL/BFLDH instructions
B0
CORE.3
Incorrect instruction fetch on Cache Jump
B0
CORE.4
Incorrect instruction fetch on Jump to itself
B0
CLK.1
ADAPT mode entered during power-up synchronous reset
B0
DAD.6
Incorrect PEC source fetch after JMPS instruction
B0
DAD.7
Incorrect pipeline dependency detection between DPRAM and
(E)SFR address space
B0


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