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ST10F280-AB Scheda tecnica(PDF) 3 Page - STMicroelectronics |
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ST10F280-AB Scheda tecnica(HTML) 3 Page - STMicroelectronics |
3 / 4 page ST10F280-AB 3/4 2.4 - ST_XTIMER.01 - XADCINJ Signal Output Too Short for ADC Channel Injection The duration of the XADCINJ output lasts two cycles (50ns at 40MHz) but to ensure that a signal transition is properly recognized, an external capture input signal should be held for at least 8 CPU clock cycles before it changes its level so the duration of the XADCINJ signal is too short. Workaround: The falling edge of the XADCINJ signal must be delayed up to 8 CPU clock cycles. History of Fixed Functional Problems of the ST10F280 Summary of Remaining Functional Problems Known on the ST10F280-AB Figure 1 : XADCINJ Timing Figure 2 : External Connection for ADC Channel Injection Name Short Description Fixed in Step ST_XADCMUX.01 Erroneous Conversion Result in Overload Condition AB Name Short Description PWRDN.1 Execution of PWRDN Instruction MAC.9 CoCMP Instruction Inverted Operands MAC.10 E Flag Evaluation for CoSHR and CoASHR Instructions when Saturation Mode is Enabled ST_XTIMER.01 XADCINJ Signal Output Too Short for ADC Channel Injection XCLK XADCINJ 4 TCL = 50ns Input Latch XTIMER Clock P7.7/CC31 XADCINJ CAPCOM2 UNIT C R Output trigger for ADC channel injection Typical value: R = 10K Ω C = 47pF at 40MHz |
Codice articolo simile - ST10F280-AB |
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