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ST10F168-Q6 Scheda tecnica(PDF) 8 Page - STMicroelectronics |
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ST10F168-Q6 Scheda tecnica(HTML) 8 Page - STMicroelectronics |
8 / 74 page ST10F168 8/74 P4.0 - P4.7 85-92 I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. For external bus configuration, Port 4 can be used to output the segment address lines: 85-89 O P4.0-P4.4 A16-A20 Segment Address Line 90 O P4.5 A21 Segment Address Line I CAN_RxD CAN Receiver Data Input 91 O P4.6 A22 Segment Address Line O CAN_TxD CAN Transmitter Data Output 92 O P4.7 A23 Most Significant Segment Addrress Line RD 95 O External Memory Read Strobe. RD is activated for every external instruction or data read access. WR/WRL 96 O External Memory Write Strobe. In WR-mode this pin is activated for every external data write access. In WRL mode this pin is activated for low Byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in the SYSCON register for mode selection. READY/ READY 97 I Ready Input. The active level is programmable. When the Ready function is enabled, the selected inactive level at this pin, during an external memory access, will force the insertion of wait state cycles until the pin returns to the selected active level. ALE 98 O Address Latch Enable Output. In case of use of external addressing or of multi- plexed mode, this signal is the latch command of the address lines. EA 99 I External Access Enable pin. A low level at this pin during and after Reset forces the ST10F168 to start the program from the external memory space. A high level forces the ST10F168 to start in the internal memory space. P0L.0 - P0L.7 P0H.0 P0H.1 - P0H.7 100 - 107, 108, 111 - 117 I/O Two 8-bit bidirectional I/O ports P0L and P0H, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. In case of an external bus configuration, Port0 serves as the address (A) and as the address / data (AD) bus in multiplexed bus modes and as the data (D) bus in demul- tiplexed bus modes. Table 1 : Pin Description (continued) Symbol Pin Type Function Demultiplexed bus modes Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: D0 – D7 D0 - D7 P0H.0 – P0H.7: I/O D8 - D15 Multiplexed bus modes Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7 P0H.0 – P0H.7: A8 – A15 AD8 – AD15 |
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