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RIVA128 Scheda tecnica(PDF) 8 Page - STMicroelectronics |
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RIVA128 Scheda tecnica(HTML) 8 Page - STMicroelectronics |
8 / 77 page 128-BIT 3D MULTIMEDIA ACCELERATOR RIVA 128 8/77 2.3 SGRAM FRAMEBUFFER INTERFACE 2.4 VIDEO PORT PCIGNT# I Grant. This signal indicates to the RIVA 128 that access to the bus has been granted and it can now become bus master. When connected to AGP additional information is provided on AGPST[2:0] indicating that the master is the recipient of previously requested read data (high or low priority), it is to provide write data (high or low priority), for a previously enqueued write command or has been given permission to start a bus transaction (AGP or PCI). PCIINTA# O Interrupt request line. This open drain output is asserted and deasserted asynchronously to PCICLK. Signal I/O Description FBD[127:0] I/O The 128-bit SGRAM memory data bus. FBD[31:0] are also used to access up to 64KBytes of 8-bit ROM or Flash ROM, using FBD[15:0] as address ROMA[15:0], FBD[31:24] as ROMD[7:0], FBD[17] as ROMWE# and FBD[16] as ROMOE#. FBA[10:0] O Memory Address bus. Configuration strapping options are also decoded on these signals during PCIRST# as described in Section 10, page 49. [FBA[10] is reserved for future expansion and should be pulled to GND via a 4.7K Ω resistor. FBRAS# O Memory Row Address Strobe for all memory devices. FBCAS# O Memory Column Address Strobe for all memory devices. FBCS[1:0]# O Memory Chip Select strobes for each SGRAM bank. FBWE# O Memory Write Enable strobe for all memory devices. FBDQM[15:0] O Memory Data/Output Enable strobes for each of the 16 bytes. FBCLK0, FBCLK1, FBCLK2 O Memory Clock signals. Separate clock signals FBCLK0 and FBCLK1 are provided for each bank of SGRAM for reduced clock skew and loading. FBCLK2 is fed back to FBCLKFB. Details of recommended memory clock layout are given in Section 6.3, page 31. FBCLKFB I Framebuffer clock feedback. FBCLK2 is fed back to FBCLKFB. FBCKE ∗ O This signal is currently a “no-connect” in this revision of the RIVA 128 but may be activated to support the framebuffer memory clock enable for power management in future pin com- patible devices. It is recommended that this pin is tied to VDD through a 4.7K Ω pull-up resistor. Signal I/O Description MP_AD[7:0] I/O Media Port 8-bit multiplexed address and data bus or ITU-R-656 video data bus when in 656 mode. MPCLK I 40MHz Media Port system clock or pixel clock when in 656 mode. MPDTACK# I Media Port data transfer acknowledgment signal. MPFRAME# O Initiates Media Port transfers when active, terminates transfers when inactive. MPSTOP# I Media Port control signal used by the slave to terminate transfers. Signal I/O Description |
Codice articolo simile - RIVA128 |
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Descrizione simile - RIVA128 |
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