6
STP2223BGA
UPA to PCI Interface
U2P
July 1997
Functional Block Overviews
This section gives a brief description of each top level functional block. A more detailed description of each
block can be found in the U2P Users Manual. Each block is described in its own individual chapter in the U2P
Users Manual. The top level blocks in U2P fall into one of five categories:
•UPA.
• PCI.
• Interrupt.
• Internal Control.
• Miscellaneous.
UPA Interface blocks
The UPA is UltraSPARC’s packet switched main system bus. In an UltraSPARC system, the UPA can operate
up to 100 MHz. Data and address have independent flow controls. Each type of UPA cycle (PIO read, PIO
write, DMA read, etc.) uses its own FIFO-based queueing. There is a synchronization boundary between the
UPA interface blocks and other U2P blocks, which run at 66.7 MHz.
• UPA Master/Slave: This block deals exclusively with UPA address control. It listens to UPA_A when U2P
is a slave. It also arbitrates for and drives UPA_A when U2P is a master.
• UPA_Reply: This block deals exclusively with UPA data. It generates P_REPLY to the System Controller
(SC) ASIC during PIO and copyback cycles. It also listens to S_REPLY from the SC and manages the UPA
data FIFO’s accordingly.
• ECC Generate: Generates ECC on the outgoing 64-bit UPA data path.
• ECC Check: Checks ECC on the incoming 64-bit UPA data path.
PCI Interface blocks
• PBM (PCI Bus Module): This is the main portion of the PCI interface. U2P contains two nearly identical
copies of this block. One is designed to support a 64-bit PCI bus at 66 MHz or 33 MHz with up to four
master devices. The other supports a 64-bit PCI bus at 33MHz with up to six master devices. The PBM
adheres to all PCI protocol guidelines as contained in the PCI Revision 2.1 specification. Each PBM controls
arbitration, flow control and error handling for its bus segment. Each PBM also handles the big- to
little-endian byte twisting required for correct operation of both PIO and DVMA datapaths.
• IOMMU: For the portion of the PCI memory address space which is reserved for DMA to the UPA bus, the
IOMMU maps the PCI address into the appropriate UPA physical address. The IOMMU keeps the 16 most
recently used translations in a TLB, and automatically performs hardware tablewalks on TLB misses. There
is a single IOMMU supporting both PCI busses. Only a single translation can be in progress at a time, and
during tablewalks, translations from the other bus segment will be delayed.
• Streaming Cache: The Streaming Cache (STC) is used to accelerate PCI DMA activity. For DMA reads, the
STC will speculatively prefetch 64-byte cache lines. For DMA writes, the STC buffers up 64-byte lines
before sending to the UPA interface. There are two separate STC blocks in U2P, one associated with each
PBM block. Each STC contains storage for 16 virtual address tagged entries and their data, which is stored
in 64-byte lines, allocated on a least recently used basis.
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