M41T00 datasheet(8/15 Pages) STMICROELECTRONICS

Il numero della parte	M41T00

Spiegazioni elettronici	Serial Access TIMEKEEPER

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Produttore elettronici	STMICROELECTRONICS [STMicroelectronics]

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M41T00

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Figure 6. Serial Bus Data Transfer Sequence

Figure 7. Acknowledgment Sequence

AI00587

DATA

CLOCK

DATA LINE

STABLE

DATA VALID

START

CONDITION

CHANGE OF

DATA ALLOWED

STOP

CONDITION

AI00601

DATA OUTPUT

BY RECEIVER

DATA OUTPUT

BY TRANSMITTER

SCLK FROM

MASTER

START

CLOCK PULSE FOR

ACKNOWLEDGEMENT

12

89

MSB

LSB

CLOCK OPERATION

The eight byte clock register (see Table 3) is used

to both set the clock and to read the date and time

from the clock, in a binary coded decimal format.

Seconds, Minutes, and Hours are contained within

the first three registers. Bits D6 and D7 of clock

register 2 (Hours Register) contain the CENTURY

ENABLE Bit (CEB) and the CENTURY Bit (CB).

Setting CEB to a ’1’ will cause CB to toggle, either

from ’0’ to ’1’ or from ’1’ to ’0’ at the turn of the cen-

tury (depending upon its initial state). If CEB is set

to a ’0’, CB will not toggle. Bits D0 through D2 of

register 3 contain the Day (day of week). Registers

4, 5 and 6 contain the Date (day of month), Month

and Years. The final register is the Control Regis-

ter (this is described in the Clock Calibration sec-

tion). Bit D7 of register 0 contains the STOP Bit

(ST). Setting this bit to a ’1’ will cause the oscillator

to stop. If the device is expected to spend a signif-

icant amount of time on the shelf, the oscillator

may be stopped to reduce current drain. When re-

set to a ’0’ the oscillator restarts within one second.

The seven Clock Registers may be read one byte

at a time, or in a sequential block. The Control

Register (Address location 7) may be accessed in-

dependently. Provision has been made to assure

that a clock update does not occur while any of the

seven clock addresses are being read. If a clock

address is being read, an update of the clock reg-

isters will be delayed by 250ms to allow the read

to be completed before the update occurs. This

will prevent a transition of data during the read.

Note: This 250ms delay affects only the clock reg-

ister update and does not alter the actual clock

time.

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