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TS4855 Scheda tecnica(PDF) 3 Page - STMicroelectronics

Il numero della parte TS4855
Spiegazioni elettronici  LOUDSPEAKER & HEADSET DRIVER WITH VOLUME CONTROL
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Produttore elettronici  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

TS4855 Scheda tecnica(HTML) 3 Page - STMicroelectronics

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SPI Bus Interface
TS4855
3/27
2
SPI BUS INTERFACE
2.1 Pin Descriptions
2.2 SPI Operation Description
The serial data bits are organized into a field
containing 8 bits of data as shown in Table 1. The
DATA 0 to DATA 2 bits determine the output
mode of the TS4855 as shown in Table 2. The
DATA 3 to DATA 7 bits determine the gain level
setting as illustrated by Table 3. For each SPI
transfer, the data bits are written to the DATA pin
with the least significant bit (LSB) first. All serial
data are sampled at the rising edge of the CLK
signal. Once all the data bits have been sampled,
ENB transitions from logic-high to logic low to
complete the SPI sequence. All 8 bits must be
received before any data latch can occur. Any
excess CLK and DATA transitions will be ignored
after the height rising clock edge has occurred.
For any data sequence longer than 8 bits, only the
first 8 bits will get loaded into the shift register and
the rest of the bits will be disregarded.
(SD = Shut Down Mode, PHS = Non Filtered Phone In HS, PIHF = External High Pass Filtered Phone In IHF)
Pin
Functional Description
DATA
This is the serial data input pin
CLK
This is the clock input pin
ENB
This is the SPI enable pin active at high level
Table 1: Bit Allocation
DATA
MODES
LSB
DATA 0
Mode 1
DATA 1
Mode 2
DATA 2
Mode 3
DATA 3
gain 1
DATA 4
gain 2
DATA 5
gain 3
DATA 6
gain 4
MSB
DATA 7
gain 5
Table 2: Output Mode Selection
Output
Mode #
DATA 2
DATA 1
DATA 0
SPKRout
Rout
Lout
0
0
0
0
SD
SD
SD
10
0
1
+12dBxPIHF
SD
SD
20
1
0
MUTE
G1xPHS
G1xPHS
30
1
1
+12dBxPIHF
G1xPHS
G1xPHS
41
0
0
MUTE
G2xRin
G2xLin
51
0
1
+12dBxPIHF
G2xRin
G2xLin
61
1
0
MUTE
G1xPHS+
G2xRin
G1xPHS+
G2xLin
71
1
1
+12dBxPIHF
G1xPHS+
G2xRin
G1xPHS+
G2xLin


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