7-440

CD4073BMS, CD4081BMS, CD4082BMS

FIGURE 5. SCHEMATIC DIAGRAM FOR CD4082BMS (1 OF 2 IDENTICAL GATES)

FIGURE 6. LOGIC DIAGRAM FOR CD4082BMS (1 OF 2 IDENTICAL GATES)

Typical Performance Characteristics

FIGURE 7. TYPICAL VOLTAGE TRANSFER

CHARACTERISTICS

FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A

FUNCTION OF LOAD CAPACITANCE

n

p

ALL INPUTS PROTECTED BY

*

CMOS PROTECTION NETWORK

*

3 (11)

p

VDD

n

p

*

2 (12)

n

p

n

n

p

n

p

p

VDD

VSS

n

p

*

4 (10)

p

VSS

n

p

*

5 (9)

n

p

n

VSS

n

VDD

VSS

J

1 (13)

3 (11)

2 (12)

D

C

5 (9)

4 (10)

B

A

10V

5V

5

SUPPLY VOLTAGE (VDD) = 15V

0

5

10

15

20

25

10

15

20

INPUT VOLTAGE (VIN) (V)

10V

5V

50

SUPPLY VOLTAGE (VDD) = 15V

10

LOAD CAPACITANCE (CL) (pF)

25

75

100

125

150

175

200

0

2030

40

50

6070

80

90

100