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AD5626BCPZ Scheda tecnica(PDF) 4 Page - Analog Devices |
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AD5626BCPZ Scheda tecnica(HTML) 4 Page - Analog Devices |
4 / 20 page AD5626 Rev. 0 | Page 4 of 20 TIMING CHARACTERISTICS @ VDD = 5.0 V ± 5%, −40°C ≤ TA ≤ +85°C, unless otherwise noted. Table 2. Parameter1, 2 Limit at TMIN, TMAX Unit Description tCH 30 ns min Clock width high tCL 30 ns min Clock width low tLDW 20 ns min Load pulse width tDS 15 ns min Data setup tDH 15 ns min Data hold tCLRW 30 ns min Clear pulse width tLD1 15 ns min Load setup tLD2 10 ns min Load hold tCSS 30 ns min Select tCSH 20 ns min Deselect 1 These parameters are guaranteed by design and not subject to production testing. 2 All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. Timing Diagram SDIN D11 D10 D9 D8 D7 D6 D5 D4 ±1 LSB ERROR BAND D3 D2 D1 DO tCSH tLD2 SCLK CS LDAC tLD1 tCL tDS tCH tDH tS tS tCLRW tLDW tCSS SDIN SCLK LDAC CLR FS VOUT ZS Figure 2. Timing Diagram |
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