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FDG332PZ Scheda tecnica(PDF) 4 Page - Fairchild Semiconductor |
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FDG332PZ Scheda tecnica(HTML) 4 Page - Fairchild Semiconductor |
4 / 6 page www.fairchildsemi.com 4 ©2007 Fairchild Semiconductor Corporation FDG332PZ Rev.B Figure 7. 0 246 8 0.0 1.5 3.0 4.5 ID = -2.6A VDD = -15V VDD = -5V Qg, GATE CHARGE (nC) VDD = -10V Gate Charge Characteristics Figure8. 0.1 1 10 100 1000 30 20 f = 1MHz VGS = 0V -VDS, DRAIN TO SOURCE VOLTAGE (V) Crss Coss Ciss CapacitancevsDrain to Source Voltage Figure 9. 0.1 1 10 0.01 0.1 1 10 10s 1s 100ms DC 10ms 1ms 100us THIS AREA IS LIMITED BY rDS(on) 50 SINGLE PULSE TJ = MAX RATED RθJA = 260 oC/W TA = 25oC -VDS, DRAIN to SOURCE VOLTAGE (V) Forward Bias Safe Operating Area Figure 10. 0 5 10 15 20 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 VGS = 0V TJ = 25oC TJ = 150oC -VGS, GATE TO SOURCE VOLTAGE (V) Gate Leakage Current vs Gate to Source Voltage Figure 11. Transient Thermal Response Curve 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 0.1 1 10 100 V GS = -4.5V SINGLE PULSE RθJA = 260 oC/W T A = 25 oC t, PULSE WIDTH (s) Typical Characteristics T J = 25°C unless otherwise noted |
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