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74LV138 Scheda tecnica(PDF) 9 Page - NXP Semiconductors |
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74LV138 Scheda tecnica(HTML) 9 Page - NXP Semiconductors |
9 / 17 page 74LV138_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 November 2007 9 of 17 NXP Semiconductors 74LV138 3-to-8 line decoder/demultiplexer; inverting Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. Fig 8. Load circuit for switching times VCC VI VO 001aaa663 D.U.T. CL 50 pF RT RL 1 k Ω PULSE GENERATOR Table 9. Test data Supply voltage VCC Input VI tr, tf < 2.7 V VCC ≤ 2.5 ns 2.7 V to 3.6 V 2.7 V ≤ 2.5 ns ≥ 4.5 V VCC ≤ 2.5 ns |
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