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74LV32 Scheda tecnica(PDF) 7 Page - NXP Semiconductors |
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74LV32 Scheda tecnica(HTML) 7 Page - NXP Semiconductors |
7 / 15 page 74LV32_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 November 2007 7 of 15 NXP Semiconductors 74LV32 Quad 2-input OR gate 11. Waveforms Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. The input (nA, nB) to output (nY) propagation delays mna244 tPHL tPLH VM VM nA, nB input nY output GND VI Table 8. Measurement points Supply voltage Input Output VCC VM VM < 2.7 V 0.5VCC 0.5VCC 2.7 V to 3.6 V 1.5 V 1.5 V ≥ 4.5 V 0.5VCC 0.5VCC Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. Fig 7. Load circuit for switching times VCC VI VO 001aaa663 D.U.T. CL 50 pF RT RL 1 k Ω PULSE GENERATOR Table 9. Test data Supply voltage VCC Input VI tr, tf < 2.7 V VCC ≤ 2.5 ns 2.7 V to 3.6 V 2.7 V ≤ 2.5 ns ≥ 4.5 V VCC ≤ 2.5 ns |
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