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FDG8850NZ Scheda tecnica(PDF) 1 Page - Fairchild Semiconductor |
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FDG8850NZ Scheda tecnica(HTML) 1 Page - Fairchild Semiconductor |
1 / 5 page tm April 2007 ©2007 Fairchild Semiconductor Corporation FDG8850NZ Rev.B www.fairchildsemi.com 1 FDG8850NZ Dual N-Channel PowerTrench® MOSFET 30V,0.75A,0.4 Ω Features Max rDS(on) = 0.4Ω at VGS = 4.5V, ID = 0.75A Max rDS(on) = 0.5Ω at VGS = 2.7V, ID = 0.67A Very low level gate drive requirements allowing operation in 3V circuits(VGS(th) <1.5V) Very small package outline SC70-6 RoHS Compliant General Description This dual N-Channel logic level enhancement mode field effect transistors are produced using Fairchild’s proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs. Since bias resistors are not required, this dual digital FET can replace several different digital transistors, with differ- ent bias resistor values. MOSFET Maximum Ratings T A = 25°C unless otherwise noted Thermal Characteristics Package Marking and Ordering Information Symbol Parameter Ratings Units VDS Drain to Source Voltage 30 V VGS Gate to Source Voltage ±12 V ID Drain Current -Continuous 0.75 A -Pulsed 2.2 PD Power Dissipation for Single Operation (Note 1a) (Note 1b) 0.36 W 0.30 TJ, TSTG Operating and Storage Junction Temperature Range –55 to +150 °C RθJA Thermal Resistance, Junction to Ambient Single operation (Note 1a) 350 °C/W RθJA Thermal Resistance, Junction to Ambient Single operation (Note 1b) 415 Device Marking Device Reel Size Tape Width Quantity .50 FDG8850NZ 7” 8mm 3000 units S1 G1 D2 D1 G2 S2 S1 S2 G2 D1 D2 G1 Pin 1 SC70-6 Q1 Q2 |
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