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SM320C6701GLPS16 Scheda tecnica(PDF) 3 Page - Texas Instruments |
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SM320C6701GLPS16 Scheda tecnica(HTML) 3 Page - Texas Instruments |
3 / 64 page SMJ320C6701 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SGUS030B – APRIL 2000 – REVISED MAY 2001 3 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 device characteristics Table 1 provides an overview of the ’C6701 DSP. The table shows significant features of each device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count. Table 1. Characteristics of the ’C6701 Processors CHARACTERISTICS DESCRIPTION Device Number SMJ320C6701 On-Chip Memory 512-Kbit Program Memory 512-Kbit Data Memory (organized as 2 blocks) Peripherals 2 Mutichannel Buffered Serial Ports (McBSP) 2 General-Purpose Timers Host-Port Interface (HPI) External Memory Interface (EMIF) Cycle Time 7 ns at 140 MHz, and 6 ns at 167 MHz Package Type 27 mm × 27 mm, 429-Pin BGA (GLP) Nominal Voltage 1.9 V Core 3.3 V I/O functional and CPU block diagram Control Logic Test ’C67x CPU Data Path B B Register File Program Access/Cache Controller Instruction Fetch Instruction Dispatch Instruction Decode Data Path A A Register File Data Access Controller Power- Down Logic .L1† .S1† .M1† .D1 .D2 .M2† .S2† .L2† 32 ROM/FLASH SRAM I/O Devices 16 Timer 0 Timer 1 External Memory Interface (EMIF) Multichannel Buffered Serial Port 0 Multichannel Buffered Serial Port 1 Direct Memory Access Controller (DMA) (4 Channels) Host Port Interface (HPI) Internal Program Memory 1 Block Program/Cache (64K Bytes) Control Registers Internal Data Memory (64K Bytes) 2 Blocks of 8 Banks Each In-Circuit Emulation Interrupt Control Framing Chips: H.100, MVIP, SCSA, T1, E1 AC97 Devices, SPI Devices, Codecs ’C6701 Digital Signal Processor PLL (x1, x4) SBSRAM SDRAM HOST CONNECTION MC68360 Glueless MPC860 Glueless PCI9050 Bridge + Inverter MC68302 + PAL MPC750 + PAL MPC960 (Jx/Rx) + PAL † These functional units execute floating-point instructions. |
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