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MC13158FTB Scheda tecnica(PDF) 6 Page - LANSDALE Semiconductor Inc. |
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MC13158FTB Scheda tecnica(HTML) 6 Page - LANSDALE Semiconductor Inc. |
6 / 23 page ML13158 LANSDALE Semiconductor, Inc. GENERAL The ML13158 is a low power single conversion wideband FM receiver incorporating a split IF. This device can be used as the backend in digi- tal FM systems such as Digital European Cordless Telephone (DECT) and wide band data links with data rates up to 2.0 Mbps. It contains a mixer, oscillator, Received Signal Strength Indicator (RSSI), IF ampli- fier, limiting IF, quadrature detector, power down or enable function, and a data slicer with output off function. Further details are covered in the Pin Function Description which shows the equivalent internal cir- cuit and external circuit requirements. CURRENT REGULATION Temperature compensating voltage independent current regulators which are controlled by the enable pin (Pin 25) where “low” pow- ers up and “high” powers down the entire circuit. MIXER The mixer is a double–balanced four quadrant multiplier and is designed to work up to 500 MHz. It can be used in differential or in single–ended mode by connecting the other input to the positive supply rail. The linear gain of the mixer is approximately 22 dB at 100 mVrms LO drive level. The mixer gain and noise figure have been emphasized at the expense of intermodulation performance. RSSI measurements are added in the mixer to extend the range to higher signal levels. The single–ended parallel equivalent input impedance of the mixer is Rp ~ 1.0 k Ω and Cp ~ 2.0 pF. The buffered output of the mixer is internally loaded resulting in an out- put impedance of 330 Ω. LOCAL OSCILLATOR The on–chip transistor operates with crystal and LC resonant ele- ments up to 220 MHz. Series resonant, overtone crystals are used to achieve excellent local oscillator stability. Third overtone crys- tals are used through about 65 to 70 MHz. Operation from 70 MHz up to 180 MHz is feasible using the on–chip transistor with a 5th or 7th overtone crystal. To enhance operation using an overtone crystal, the internal transistor bias is increased by adding an exter- nal resistor from Pin 29 to VEE, however, with an external resistor, the oscillator stays on during power down. Typically, –10 dBm of local oscillator drive is needed to adequately drive the mixer. With an external oscillator source, the IC can be operated up to 500 MHz. RSSI The Received Signal Strength Indicator (RSSI) output is a current proportional to the log of the received signal amplitude. The RSSI current output is derived by summing the currents from the mixer, IF and limiting amplifier stages. An increase in RSSI dynamic range, particularly at higher input signal levels is achieved. The RSSI circuit is designed to provide typically 85 dB of dynamic range with temperature compensation. Linearity of the RSSI is optimized by using external ceramic band- pass filters which have an insertion loss of 4.0 dB and 330 Ω source and load impedance. For higher data rates used in DECT and related applications, LC bandpass filtering is necessary to acquire the desired bandpass response; however, the RSSI linearity will require the same insertion loss. RSSI BUFFER The RSSI output current creates a voltage across an external resis- tor. A unity voltage–gain amplifier is used to buffer this voltage. The output of this buffer has an active pull–up but no pull–down, so it can also be used as a peak detector. The negative slew rate is determined by external capacitance and resistance to the negative supply. IF AMPLIFIER The first IF amplifier section is composed of three differential stages with the second and third stages contributing to the RSSI. This section has internal DC feedback and external input decou- pling for improved symmetry and stability. The total gain of the IF amplifier block is approximately 40 dB at 10.7 MHz. The fixed internal input impedance is 330 Ω. When using ceramic filters requiring source and loss impedances of 330 Ω, no external matching is necessary. Overall RSSI linearity is dependent on hav- ing total midband attenuation of 10 dB (4.0 dB insertion loss plus 6.0 dB impedance matching loss) for the filter. The output of the IF amplifier is buffered and the impedance is 330 Ω. LIMITER The limiter section is similar to the IF amplifier section except that five differential stages are used. The fixed internal input impedance is 330 Ω. The total gain of the limiting amplifier section is approxi- mately 70 dB. This IF limiting amplifier section internally drives the quadrature detector section and it is also brought out on Pin 12. QUADRATURE DETECTOR The quadrature detector is a doubly balanced four quadrant multi- plier with an internal 5.0 pF quadrature capacitor between Pins 12 and 13. An external capacitor may be added between these pins to increase the IF signal to the external parallel RLC resonant circuit that provides the 90 degree phase shift and drives the quadrature detector. A single pin (Pin 13) provides for the external LC parallel resonant network and the internal connection to the quadrature detector. Internal low pass filter capacitors have been selected to control the bandwidth of the detector. The recovered signal is brought out by the inverting amplifier buffer. An external feedback resistor from the output (Pin 17) to the output amplitude; it is combined with another external resistor from the input to the negative supply (Pin 15) controls the output amplitude; it is combined with another external resistor from the input to the negative supply (Pin 16) to set the output DC level. For a resistor ratio of 1, the DC level at the detector output is 2.0 VBE (see Figure 12). A small capacitor C17 across the first resistor (from Pin 17 to 15) can be used to reduce the bandwidth. DATA SLICER The data slicer is a comparator that is designed to square up the data signal. Across the data slicer inputs (Pins 18 and 20) are back to back diodes. The recovered data signal from the quadrature detector can be DC coupled to the data slicer DS IN1 (Pin 18). In the application cir- cuit shown in Figure 1 it will be centered at 2.0 VBE and allowed to swing ± VBE. A capacitor is placed from DS IN2 (Pin 20) to VEE. The size of this capacitor and the nature of the data slicer shapes up the recovered signal. The time constant is short for large peak to peak voltage swings or when there is a change in DC level at the detector output. For small signal or for continuous bits of the same polarity which drift close to the threshold voltage, the time CIRCUIT DESCRIPTION www.lansdale.com Page 6 of 23 Issue B |
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