tm

April 2007

©2007 Fairchild Semiconductor Corporation

FDG8842CZ Rev.B

www.fairchildsemi.com

1

FDG8842CZ

Q1:30V,0.75A,0.4

Ω; Q2:–25V,–0.41A,1.1Ω

Features

Q1: N-Channel

Q2: P-Channel

Very low level gate drive requirements allowing direct

Very small package outline SC70-6

RoHS Compliant

General Description

These N & P-Channel logic level enhancement mode field effect

transistors are produced using Fairchild’s proprietary, high cell

density, DMOS technology. This very high density process is

especially tailored to minimize on-state resistance. This

device has been designed especially for low voltage applica-

tions as a replacement for bipolar digital transistors and small

signal MOSFETs. Since bias resistors are not required, this dual

digital FET can replace several different digital transistors, with

different bias resistor values.

Thermal Characteristics

Package Marking and Ordering Information

Symbol

Parameter

Q1

Q2

Units

Drain to Source Voltage

30

–25

V

Gate to Source Voltage

±12

–8

V

Drain Current

-Continuous

0.75

–0.41

A

-Pulsed

2.2

–1.2

Power Dissipation for Single Operation

(Note 1a)

(Note 1b)

0.36

W

0.30

Operating and Storage Junction Temperature Range

–55 to +150

°C

Thermal Resistance, Junction to Ambient Single operation

(Note 1a)

350

°C/W

Thermal Resistance, Junction to Ambient Single operation

(Note 1b)

415

Device Marking

Device

Reel Size

Tape Width

Quantity

.42

FDG8842CZ

7”

8mm

3000 units

S1

G1

D2

D1

G2

S2

S1

S2

G2

D1

D2

G1

Pin 1

SC70-6

Q1

Q2