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FDG8842CZ Scheda tecnica(PDF) 1 Page - Fairchild Semiconductor |
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FDG8842CZ Scheda tecnica(HTML) 1 Page - Fairchild Semiconductor |
1 / 8 page tm April 2007 ©2007 Fairchild Semiconductor Corporation FDG8842CZ Rev.B www.fairchildsemi.com 1 FDG8842CZ Complementary PowerTrench® MOSFET Q1:30V,0.75A,0.4 Ω; Q2:–25V,–0.41A,1.1Ω Features Q1: N-Channel Max rDS(on) = 0.4Ω at VGS = 4.5V, ID = 0.75A Max rDS(on) = 0.5Ω at VGS = 2.7V, ID = 0.67A Q2: P-Channel Max rDS(on) = 1.1Ω at VGS = –4.5V, ID = –0.41A Max rDS(on) = 1.5Ω at VGS = –2.7V, ID = –0.25A Very low level gate drive requirements allowing direct operation in 3V circuits(VGS(th) <1.5V) Very small package outline SC70-6 RoHS Compliant General Description These N & P-Channel logic level enhancement mode field effect transistors are produced using Fairchild’s proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applica- tions as a replacement for bipolar digital transistors and small signal MOSFETs. Since bias resistors are not required, this dual digital FET can replace several different digital transistors, with different bias resistor values. MOSFET Maximum Ratings T A = 25°C unless otherwise noted Thermal Characteristics Package Marking and Ordering Information Symbol Parameter Q1 Q2 Units VDS Drain to Source Voltage 30 –25 V VGS Gate to Source Voltage ±12 –8 V ID Drain Current -Continuous 0.75 –0.41 A -Pulsed 2.2 –1.2 PD Power Dissipation for Single Operation (Note 1a) (Note 1b) 0.36 W 0.30 TJ, TSTG Operating and Storage Junction Temperature Range –55 to +150 °C RθJA Thermal Resistance, Junction to Ambient Single operation (Note 1a) 350 °C/W RθJA Thermal Resistance, Junction to Ambient Single operation (Note 1b) 415 Device Marking Device Reel Size Tape Width Quantity .42 FDG8842CZ 7” 8mm 3000 units S1 G1 D2 D1 G2 S2 S1 S2 G2 D1 D2 G1 Pin 1 SC70-6 Q1 Q2 |
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