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TMPN3120FE3MG Scheda tecnica(PDF) 4 Page - Toshiba Semiconductor |
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TMPN3120FE3MG Scheda tecnica(HTML) 4 Page - Toshiba Semiconductor |
4 / 10 page TMPN3120FE3MG 4 2005-11-29 Block Diagram Item TMPN3120FE3MG CPU 8-bit CPU × 3 RAM 2,048 bytes ROM 16,384 bytes EEPROM 2,048 bytes 16-bit timer/counter 2 channels External memory interface Not available Package 32-pin SOP Network communications port • Application I/O • General-purpose I/O • Parallel I/O • Serial I/O • Two timer/counters Etc. Clock and control 50 ms reset (min) Low-voltage detector reset circuit |
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