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N08M1618L1AB Scheda tecnica(PDF) 2 Page - AMI SEMICONDUCTOR |
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N08M1618L1AB Scheda tecnica(HTML) 2 Page - AMI SEMICONDUCTOR |
2 / 11 page Stock No. 23211-03 9/21/06 ADVANCE INFORMATION 2 The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. N08M1618L1A Advance Information AMI Semiconductor, Inc. Functional Block Diagram Functional Description CE1 CE2 WE OE UB LB I/O0 - I/O151 1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - I/O7 are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown. MODE POWER H X XX XX High Z Standby2 2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally isolated from any external influence and disabled from exerting any influence externally. Standby X L XX XX High Z Standby2 Standby XX XX H H High Z Standby2 Standby LHL X3 3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit. L1 L1 Data In Write3 Active -> Standby4 4. The device will consume active power in this mode whenever addresses are changed. Data inputs are internally isolated from any expernal influence. LH HL L1 L1 Data Out Read Active -> Standby4 LH H H L1 L1 High Z Active Standby4 Capacitance1 1. These parameters are verified in device characterization and are not 100% tested Item Symbol Test Condition Min Max Unit Input Capacitance CIN VIN = 0V, f = 1 MHz, TA = 25oC 8pF I/O Capacitance CI/O VIN = 0V, f = 1 MHz, TA = 25oC 8pF Address Inputs A0 - A3 Address Inputs A4 - A18 Word Address Decode Logic 32K Page x 16 word x 16 bit RAM Array Input/ Output Mux and Buffers Page Address Decode Logic Control Logic CE1 CE2 WE OE UB LB I/O0 - I/O7 I/O8 - I/O15 |
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