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TDA1387 Scheda tecnica(PDF) 5 Page - NXP Semiconductors |
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TDA1387 Scheda tecnica(HTML) 5 Page - NXP Semiconductors |
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5 / 16 page  1995 Dec 11 5 Philips Semiconductors Preliminary specification Stereo Continuous Calibration DAC (CC-DAC) TDA1387T PINNING SYMBOL PIN DESCRIPTION BCK 1 bit clock input WS 2 word selection input DATA 3 data input GND 4 ground VDD 5 supply voltage input IOL 6 left channel output REF 7 reference decoupling IOR 8 right channel output Fig.2 Pin configuration. FUNCTIONAL DESCRIPTION The basic operation of the continuous calibration DAC is illustrated in Fig.3 which shows the calibration and operation cycle. During calibration of the MOS current source (Fig.3a) transistor M1 is connected as a diode by applying a reference current. The voltage Vgs on the intrinsic gate-source capacitance Cgs of M1 is then determined by the transistor characteristics. After the drain current has been calibrated to the reference value Iref, the switch S1 is opened and S2 is switched to the other position (Fig.3b). The gate-to-source voltage Vgs of M1 is not changed because the charge on Cgs is preserved. Therefore, the drain current of M1 will still be equal to Iref and this exact duplication of Iref is now available at the OUT terminal. In the TDA1387T, 32 current sources and one spare current source are continuously calibrated (see Fig.1). The spare current source is included to allow continuous converter operation. The output of one calibrated source is connected to an 11-bit binary current divider which consists of 2048 transistors. A symmetrical offset decoding principle is incorporated and arranges the bit switching such that the zero-crossing is performed by switching only the LSB currents. The TDA1387T (CC-DAC) accepts serial input data format of 16-bit word length. Left and right data words are time multiplexed. The input data format is shown in Figs 4 and 5. With a HIGH level on the WS input, data is placed in the right input register, with a LOW level on the WS input, data is placed in the left input register. The data in the input registers are simultaneously latched to the output registers which control the bit switches. An internal bias current Ibias is added to the full scale output current IFS in order to achieve maximum dynamic range at the outputs of OP1 and OP2. The signal current IFS and the bias current Ibias are both proportional to the supply voltage VDD, and have a fixed mutual relation Abias (where Abias =Ibias/IFS). It is preferred that the non-inverting input of operational amplifiers OP1 and OP2 is tied to ground to achieve a maximum dynamic range over the supply voltage range. A decoupling capacitor C4 is recommended for enhancing the supply voltage ripple rejection of the DAC. It has no significant effect on the noise performance. |
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