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TDA1315 Scheda tecnica(PDF) 9 Page - NXP Semiconductors |
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TDA1315 Scheda tecnica(HTML) 9 Page - NXP Semiconductors |
9 / 36 page 1995 Jul 17 9 Philips Semiconductors Product specification Digital audio input/output circuit (DAIO) TDA1315H Table 1 Summary of validity and muting in the receive mode Note 1. X = don’t care. INPUT CONDITIONS(1) OUTPUTS PLL LOCKED MUTE ACTIVATED SDAUX SELECTED I2SOUT ENABLED VALIDITY BIT INVALID SD X X X no X 3-state 3-state No X X yes X 0 0 X yes X yes X 0 0 Yes no no yes 0 0 IEC Yes no no yes 1 1 IEC Yes no yes yes X 0 SDAUX When the I2S-bus output Port is disabled by pin I2SOEN in the stand-alone mode, pins WS, SCK, SD and INVALID will immediately become 3-state. If, however, this is performed in the host mode via the I2SOEN pin or the corresponding bit in the control register, only SD and INVALID will become 3-state immediately. Pins WS and SCK will only become 3-state after the rising edge of STROBE when the STROBE pulse changes the setting from receive to transmit mode. Thus in the host mode, when remaining in the receive mode, I2SOEN only influences the SD and INVALID pins. Pins WS and SCK are always enabled. When the I2S-bus output Port is re-enabled, data output will start with the beginning of a new stereo sample. Transmit mode Although the IEC subframe format supports up to 24 bits per audio sample, the number of significant bits can be selected as 16, 18, 20 or 24 via the control register. Because the I2S-bus Port then operates as a receiver, the timing has to be selected so that all data bits can be received. Any bits unused or unsupplied will be set to logic 0. The information regarding audio samples that may be unreliable or invalid has to be entered at pin INVALID simultaneously with the data input to pin SD. The timing will be the same as in the CD decoder ICs (e.g. the EFAB signal of the SAA7310, see Chapter “References”[5]. As the I2S-bus Port is used as an input, it must be disabled by the correct combination of pin I2SOEN and the corresponding bit in the control register. The pins WS and SCK are set to 3-state on the rising edge of STROBE, whenever the transmit mode is activated. I2SOEN influences only the data pin SD. This allows for three different configurations: • Transmit mode #1, I2SOEN = 1, I2SSEL = 1. In this instance, I2S-bus timing and data are derived from an external source and entered at pins WS, SCK and SD. Output will be at pin IECO, if IECOEN permits. • Transmit mode #2, I2SOEN = 1, I2SSEL = 0. In this instance, I2S-bus timing is derived from an external source and entered at pins WS and SCK and is also supplied to another I2S-bus source, such as an ADC. Data from that other I2S-bus source is entered at pin SDAUX. Output will be at pin IECO, if IECOEN permits. In this instance, I2SSEL acts as a source selector for pins SD and SDAUX. • Transmit mode #3, I2SOEN = 0, I2SSEL = 0. In this instance, I2S-bus timing is derived from an external source and entered at pins WS and SCK and is also supplied to another I2S-bus source, such as an ADC. Data from the other I2S-bus source is entered at pin SDAUX. Output will be at pin IECO, if IECOEN permits, and at pin SD. In this mode, SDAUX data is available both at the IEC output (a type of digital monitor function) and on the I2S-bus (e.g. for digital signal processing purposes). The remaining combination (I2SOEN = 0, I2SSEL = 1) is not used. WS, SCK and SD are then 3-state. Because the SDAUX input normally receives a signal from an ADC, the signal at pin INVALID will not be interpreted when this input is selected. All samples are assumed to be valid. In all transmit modes, INVALID is an input pin. |
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