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TDA1301 Scheda tecnica(PDF) 11 Page - NXP Semiconductors |
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TDA1301 Scheda tecnica(HTML) 11 Page - NXP Semiconductors |
11 / 14 page March 1994 12 Philips Semiconductors Product specification Digital servo processor (DSIC2) TDA1301T Notes 1. fsys = 4.2336 MHz; VRL = 0 V; VRH = 2.5 V (externally applied). 2. Internal reference source with 4 different output voltages. Selection is achieved via the serial interface. The given values are for an unloaded reference voltage. 3. fripple = 1 kHz; Vripple = 0.5 V (p-p). 4. Internal reference is switched OFF by serial interface. VRH is the reference input. 5. Externally applied VRH = 2.5 V and VRL = 0 V, measuring bandwidth: 200 Hz to 20 kHz, fi(ADC) = 1 kHz. 6. The gain of the ADC is defined as: GADC = fsys/Imax (counts/mA). Thus the digital output is II × GADC where: digital output is the number of pulses at the digital output in counts per second and II is the DC input current in mA. The maximum input current depends on the system frequency (fsys) and on Vref = VRH − VRL For D1 to D4: Ii(max) = 1.5 × fsys × Vref × 10−6/Ri × fsys [µA]. For R1 and R2: Ii(max) = 0.75 × fsys × Vref × 10−6/Ri × fsys [µA]. The gain tolerance is the deviation from the calculated gain regarding note 1. 7. At 10 to 90% levels with CL = 50 pF. 8. A resistor must be connected to set the gain of the oscillator circuit. The value of the resistor depends on the crystal or resonator connected to the oscillator circuit (see also Chapter “Application information” ). 9. When the TDA1301T is supplied by an external oscillator frequency, no crystal or resonator is required while the external reference resistor has different limits. Slave clock mode: XTALI VIL LOW level input voltage − − 0.5 V VIH HIGH level input voltage 2.0 − − V tH HIGH level input time relative to the clock period 45 − 55 % SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT |
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