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ST16C580IQ48 Scheda tecnica(PDF) 7 Page - Exar Corporation |
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ST16C580IQ48 Scheda tecnica(HTML) 7 Page - Exar Corporation |
7 / 39 page ST16C580 7 Rev. 1.22 GENERAL DESCRIPTION The 580 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-paral- lel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data character (character orientated protocol). Data integ- rity is insured by attaching a parity bit to the data character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip. The ST16C580 represents such an integration with greatly enhanced features. The 580 is fabricated with an advanced CMOS process. The 580 is an upward solution that provides 16 bytes of transmit and receive FIFO memory, instead of 16 bytes provided in the 16C550, or none in the 16C450. The 580 is designed to work with high speed modems and shared network environments, that require fast data processing time. Increased performance is real- ized in the 580 by the larger transmit and receive FIFO’s. This allows the external processor to handle more networking tasks within a given time. In addition, the 4 selectable levels of FIFO trigger interrupt and automatic hardware/software flow control is uniquely provided for maximum data throughput performance especially when operating in a multi-channel environ- ment. The combination of the above greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption. The 580 is capable of operation to 1.5Mbps with a 24 MHz crystal or external clock input. With a crystal of 7.3728 MHz and through a software option, the user can select data rates up to 460.8Kbps. The rich feature set of the 580 is available through internal registers. Automatic hardware/software flow control, selectable transmit and receive FIFO trigger levels, selectable TX and RX baud rates, infrared encoder/decoder interface, modem interface controls, and a sleep mode are all standard features. Following a power on reset or an external reset, the 580 is software compatible with previous generation of UARTs, 16C450 and 16C550. FUNCTIONAL DESCRIPTIONS Internal Registers The 580 provides 15 internal registers for monitoring and control. These registers are shown in Table 3 below. Twelve registers are similar to those already available in the standard 16C550. These registers function as data holding registers (THR/RHR), interrupt status and con- trol registers (IER/ISR), a FIFO control register (FCR), line status and control registers, (LCR/LSR), modem status and control registers (MCR/MSR), program- mable data rate (clock) control registers (DLL/DLM), and a user assessable scratchpad register (SPR). Beyond the general 16C550 features and capabilities, the 580 offers an enhanced feature register set (EFR, Xon/Xoff 1-2) that provides on board hardware/software flow control. Register functions are more fully described in the following paragraphs. |
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