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ST16C2552 Scheda tecnica(PDF) 1 Page - Exar Corporation |
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ST16C2552 Scheda tecnica(HTML) 1 Page - Exar Corporation |
1 / 36 page Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com ST16C2552 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO OCTOBER 2006 REV. 4.2.1 GENERAL DESCRIPTION The ST16C2552 (2552) is a dual universal asynchronous receiver and transmitter (UART). The ST16C2552 is an improved version of the PC16552 UART. The 2552 provides enhanced UART functions with 16 byte FIFOs, a modem control interface, and data rates up to 4 Mbps. Onboard status registers provide the user with error indications and operational status. System interrupts and modem control features may be tailored by external software to meet specific user requirements. Indepedendent programmable baud rate generators are privded to select transmit and receive clock rates from 50 Bps to 4 Mbps. The baud rate generator can be configured for either crystal or external clock input. An internal loop-back capability allows onboard diagnostics. The 2552 provides block mode data transfers (DMA) through FIFO controls. DMA transfer monitoring is provided through the signals TXRDY# and RXRDY#. An Alternate Function Register provides the user with the ability to initialize both UARTs concurrently. The 2552 is available in the 44-PLCC package. APPLICATIONS • Portable Appliances • Telecommunication Network Routers • Ethernet Network Routers • Cellular Data Devices • Factory Automation and Process Controls FEATURES Added feature in devices with top marking "A2 YYWW" and newer: ■ 5 Volt Tolerant Inputs • Pin-to-pin and functionally compatible to National PC16552 and Exar’s XR16L2752 and XR16C2852 • 4 Mbps transmit/receive operation (64 MHz External Clock Frequency) • 2 Independent UART Channels ■ Register Set Compatible to 16C550 ■ 16 byte Transmit FIFO to reduce the bandwidth requirement of the external CPU ■ 16 byte Receive FIFO with error tags to reduce the bandwidth requirement of the external CPU ■ 4 selectable RX FIFO Trigger Levels ■ Fixed Transmit FIFO interrupt trigger level ■ Full Modem Interface (CTS#, RTS#, DSR#, DTR#, RI#, CD#) • DMA operation and DMA monitoring via TXRDY# and RXRDY# pins • UART internal register sections A & B may be written to concurrently • Multi-Function output allows more package functions with few I/O pins • Programmable character lengths (5, 6, 7, 8) with even, odd, or no parity • Crystal oscillator or external clock input FIGURE 1. ST16C2552 BLOCK DIAGRAM MFA# (OP2A#, BAUDOUTA#, or RXRDYA#) MFB# (OP2B#, BAUDOUTB#, or RXRDYB#) XTAL1 XTAL2 Crystal Osc/Buffer TXA (or TXIRA) 8-bit Data Bus Interface UART Channel A 16 Byte TX FIFO 16 Byte RX FIFO BRG TX & RX UART Regs 3.3V or 5V VCC GND 2552BLK UART Channel B (same as Channel A) A2:A0 D7:D0 CS# CHSEL INTA INTB IOW# IOR# Reset TXRDYA# TXRDYB# CTS#A/B, RI#A/B, CD#A/B, DSR#A/B RXA (or RXIRA) Modem Control Logic DTR#A/B, RTS#A/B TXB (or TXIRB) RXB (or RXIRB) |
Codice articolo simile - ST16C2552_06 |
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Descrizione simile - ST16C2552_06 |
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