ST16C2450

xr

2.97V TO 5.5V DUART

REV. 4.0.1

10

2.10

Internal Loopback

The 2450 UART provides an internal loopback capability for system diagnostic purposes. The internal

loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.

Figure 7 shows how the modem port signals are re-configured. Transmit data from the transmit shift register

output is internally routed to the receive shift register input allowing the system to receive the same data that it

was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and

CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held to a logic 1 during loopback

test else upon exiting the loopback test the UART may detect and report a false “break” signal.

TXA/TXB

RXA/RXB

RTSA#/RTSB#

MCR bit-4=1

VCC

VCC

Transmit Shift Register

(THR/FIFO)

Receive Shift Register

(RHR/FIFO)

CTSA#/CTSB

DTRA#/DTRB#

DSRA#/DSRB#

RIA#/RIB#

CDA#/CDB#

OP1#

OP2#

RTS#

CTS#

DTR#

DSR#

RI#

CD#

VCC

OP2A#/OP2B#

VCC