ULTRACHIP
High-Voltage Mixed-Signal IC
©2000
6
Product Specifications
Name
Type
Pins
Description
CONFIGURATION PINS
PS[1:0]
C
Parallel/Serial.
Serial modes:
“LL”: serial (S8)
“LH”: 2-wire serial (I
2C)
Parallel modes:
“HL”: 8080
“HH”: 6800
VDD1
S
For configuration purpose
TEST PINS
TP3
I
Test control. Connect to GND.
TP[2:0]
I
Test control. Leave these pins open during normal use.
TST[3:1]
I/O
Test I/O pins. Leave these pins open during normal use.
HOST INTERFACE
VDD1
S
Use for configuration purpose.
CS0/A0
CS1/A1
I
Chip Select or Chip Address. In parallel mode and S8 mode, chip is
selected when CS0=”L” and CS1=”H”.
In I
2C mode, A[1:0] specifies bit 3~2 of UC1602I’s device address.
When the chip is not selected, D[7:0] will be high impedance.
RST
I
When RST=”L”, all control registers are re-initialized by their default
states and/or by their pin configurations if applicable.
When RST is not used, connect the pin to VDD1.
CD
I
Select Control data or Display data for read/write operation. CD pin is
not used in I
2C modes, connect it to VDD or VSS.
”L”: Control data
”H”: Display data
WR0
WR1
I
WR[1:0] controls the read/write operation of the host interface.
In parallel mode, WR[1:0] meaning depends on whether the interface is
in the 6800 mode or the 8080 mode.
In serial interface modes, these two pins are not used. Connect to VSS.
D0~D7
I/O
Bi-directional bus for both serial and parallel host interfaces.
In S8 mode, connect unused pins to VDD or VSS. In I2C mode, connect
D[1:0] to SCK, and D[5:2] to SDA, and D[7:6] to VDD or VSS.
PS=1x
PS=0x
D0
D0
SCK
D1
D1
D2
D2
D3
D3
SDA
D4
D4
D5
D5
D6
D6
-
D7
D7
-
In I
2C mode, SDA and SCK are in open-drain mode. Pull up resistors are
required on the bus. In COG applications, be careful to control ITO trace
resistance, as it will affect effective output level of SDA.
NOTE
•
Unless otherwise specified, connect all unused input pins and control pins to VSS.