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ADM1185 Scheda tecnica(PDF) 5 Page - Analog Devices |
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ADM1185 Scheda tecnica(HTML) 5 Page - Analog Devices |
5 / 16 page ADM1185 Rev. 0 | Page 5 of 16 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND 1 VIN1 2 VIN2 3 VIN3 4 VIN4 5 VCC 10 OUT1 9 OUT2 8 OUT3 7 PWRGD 6 ADM1185 TOP VIEW (Not to Scale) Figure 3. Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 GND Chip Ground Pin. 2 VIN1 Noninverting Input of Comparator 1. The voltage on this pin is compared with a 0.6 V reference. Can be used to monitor a voltage rail via a resistor divider. The output of this comparator is monitored by the state machine core. This input can also be driven by a logic signal to initiate a power-up sequence. 3 VIN2 Noninverting Input of Comparator 2. The voltage on this pin is compared with a 0.6 V reference. Can be used to monitor a voltage rail via a resistor divider. The output of this comparator is monitored by the state machine core. 4 VIN3 Noninverting Input of Comparator 3. The voltage on this pin is compared with a 0.6 V reference. Can be used to monitor a voltage rail via a resistor divider. The output of this comparator is monitored by the state machine core. 5 VIN4 Noninverting Input of Comparator 4. The voltage on this pin is compared with a 0.6 V reference. Can be used to monitor a voltage rail via a resistor divider. The output of this comparator is monitored by the state machine core. 6 PWRGD Active-High, Open-Drain Output. This output is pulled low once VCC = 1 V. When the voltage on each VINx input exceeds 0.6 V, the state machine moves from STATE4 to STATE5, and PWRGD is asserted. Once in State 5 (the PWRGD state), this output is driven low if the voltage on VIN1, VIN2, VIN3, or VIN4 falls below 0.6 V. 7 OUT3 Active-High, Open-Drain Output. This output is pulled low once VCC = 1 V. When the voltage on VIN3 exceeds 0.6 V, the state machine moves from STATE3 to STATE4, and OUT3 is asserted. Once the power-up sequence is complete and STATE5 (the PWRGD state) is reached, this output is driven low if the voltage on VIN1 falls below 0.6 V. 8 OUT2 Active-High, Open-Drain Output. This output is pulled low once VCC = 1 V. When the voltage on VIN2 exceeds 0.6 V, the state machine moves from STATE2 to STATE3, and OUT2 is asserted. Once the power-up sequence is complete and STATE5 (the PWRGD state) is reached, this output is driven low if the voltage on VIN1 falls below 0.6 V. 9 OUT1 Active-High, Open-Drain Output. This output is pulled low once VCC = 1 V. When the voltage on VIN1 exceeds 0.6 V, the state machine moves from STATE1 to STATE2, and OUT1 is asserted. A time delay of 190 ms (typical) is included before the assertion of this pin. Once the power-up sequence is complete and STATE5 (the PWRGD state) is reached, this output is driven low if the voltage on VIN1 falls below 0.6 V. 10 VCC Positive Supply Input Pin. The operating supply voltage range is 2.7 V to 5.5 V. |
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