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MC10EP35D Scheda tecnica(PDF) 2 Page - ON Semiconductor |
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MC10EP35D Scheda tecnica(HTML) 2 Page - ON Semiconductor |
2 / 20 page ECLSOIC8EVB http://onsemi.com 2 Figure 2. Evaluation Board Lay−up LAY−UP DETAIL 4 LAYER LAYER 1 (TOP SIDE) ROGERS 4003 0.008 in LAYER 2 (GROUND AND VEE PLANE P1) 1 OZ FR−4 0.020 in LAYER 3 (GROUND AND VCC PLANE P2) 1 OZ FR−4 0.025 in LAYER 4 (BOTTOM SIDE) SILKSCREEN (TOP SIDE) 0.062 $ 0.007 Board Layout The 8−lead SOIC evaluation board was designed to be versatile and accommodate several different configurations. The input, output, and power pin layout of the evaluation board is shown in Figure 3. The evaluation board has at least eleven possible configurable options. Table 1. list the devices and the relevant configuration that utilizes this PCB board. List of components and simple schematics are located in Figures 4 through 14. Place SMA connectors on J1 through J7, 50 W chip resistors on R1 through R7, and chip capacitors C1 through C4 according to configuration figures. (C1 and C2 are 0.01 mF and C3 and C4 are 0.1 mF). Figure 3. Evaluation Board Layout Top View Bottom View |
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