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74ABT544 Scheda tecnica(PDF) 1 Page - NXP Semiconductors |
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74ABT544 Scheda tecnica(HTML) 1 Page - NXP Semiconductors |
1 / 19 page 1. General description The 74ABT544 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT544 octal latched transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch enable (LEAB and LEBA) and output enable (OEAB and OEBA) inputs are provided for each register to permit independent control of data transfer in either direction. The outputs are guaranteed to sink 64 mA. The 74ABT544 contains two sets of eight D-type latches, with separate control pins for each set. Using data flow from A to B as an example, when the A-to-B enable (EAB) input and the A-to-B latch enable (LEAB) input are LOW, the A-to-B path is transparent. A subsequent LOW-to-HIGH transition of the LEAB signal puts the A data into the latches where it is stored and the B outputs no longer change with the A inputs. With EAB and OEAB both LOW, the 3-state B output buffers are active and invert the data present at the outputs of the A latches. Control of data flow from B to A is similar, but using the EBA, LEBA and OEBA inputs. 2. Features s Combines 74ABT640 and 74ABT373 type functions in one device s 8-bit octal transceiver with D-type latch s Back-to-back registers for storage s Separate controls for data flow in each direction s Output capability: +64 mA and −32 mA s Live insertion and extraction permitted s Power-up 3-state s Power-up reset s Latch-up protection: x JESD78: exceeds 500 mA s ESD protection: x MIL STD 883 method 3015: exceeds 2000 V x Machine model: exceeds 200 V 74ABT544 Octal latched transceiver with dual enable; inverting; 3-state Rev. 03 — 20 April 2005 Product data sheet |
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