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FDD6632 Scheda tecnica(PDF) 7 Page - Fairchild Semiconductor

Il numero della parte FDD6632
Spiegazioni elettronici  N-Channel Logic Level UltraFET짰 Trench Power MOSFET 30V, 9A, 70m?
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Produttore elettronici  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FDD6632 Scheda tecnica(HTML) 7 Page - Fairchild Semiconductor

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©2004 Fairchild Semiconductor Corporation
FDD6632 Rev. B1
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
application.
Therefore
the
application’s
ambient
temperature, TA (
oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
In using surface mount devices such as the TO-252
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild
provides
thermal
information
to
assist
the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction
temperature
or
power
dissipation.
Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2. The area, in square inches is the top copper
area including the gate and source pads.
(EQ. 1)
P
DM
T
JM
T
A
()
RθJA
-----------------------------
=
(EQ. 2)
RθJA
33.32
23.84
0.268
Area
+
()
-------------------------------------
+
=
25
50
75
100
125
0.01
0.1
1
10
Figure 21. Thermal Resistance vs Mounting
Pad Area
RθJA = 33.32 + 23.84/(0.268+Area)
AREA, TOP COPPER AREA (in2)


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