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DM74ALS652-01 Scheda tecnica(PDF) 2 Page - Fairchild Semiconductor |
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DM74ALS652-01 Scheda tecnica(HTML) 2 Page - Fairchild Semiconductor |
2 / 6 page www.fairchildsemi.com 2 Function Table H = HIGH Logic Level L = LOW Logic Level X = Don’t Care (Either LOW or HIGH Logic Levels, including transitions) H/L = Either LOW or HIGH Logic Level excluding transitions ↑ = Positive-going edge of pulse Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. Note 2: Select control = L; clocks can occur simultaneously Select control = H; clocks must be staggered in order to load both registers. Logic Diagram Inputs Data I/O (Note 1) Operation or Function GAB GBA CAB CBA SAB SBA A1 thru A8 B1 thru B8 XH ↑ H/L X X Input Not Specified Store A, Hold B LX H/L ↑ X X Not Specified Input Store B, Hold A LH ↑↑ X X Input Input Store A and B Data L H H/L H/L X X Input Input Isolation, Hold Storage L L X X X L Output Input Real-Time B Data to A Bus L L X H/L X H Output Input Stored B Data to A Bus H H X X L X Input Output Real-Time A Data to B Bus HH ↑↑ X X Input Output Stored A Data to B Bus HH ↑↑ X (Note 2) X Input Output Store A in both Registers LL ↑↑ XX (Note 2) Output Input Store B in both Registers H L H or L H or L H H Output Output Stored A Data to B Bus and Stored B Data to A Bus |
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