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74ACTQ821 Scheda tecnica(PDF) 4 Page - Fairchild Semiconductor |
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74ACTQ821 Scheda tecnica(HTML) 4 Page - Fairchild Semiconductor |
4 / 7 page www.fairchildsemi.com 4 DC Electrical Characteristics (Continued) Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: DIP package. Note 5: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND. Note 6: Maximum number of data inputs (n) switching. (n −1) inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V ILD), 0V to threshold (VIHD), f = 1 MHz. AC Electrical Characteristics Note 7: Voltage Range 5.0 is 5.0V ± 0.5V Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Not tested. AC Operating Requirements Note 9: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance VCC TA = + 25°CTA = − 40°C to + 85°C Symbol Parameter (V) CL = 50 pF CL = 50 pF Units (Note 7) Min Typ Max Min Max fMAX Maximum Clock 5.0 120 110 MHz Frequency tPLH Propagation Delay 5.0 3.0 6.5 9.5 2.5 10.5 ns tPHL CP to On tPZH Output Enable Time 5.0 3.0 7.5 10.5 2.5 11.5 ns tPZL OE to On tPHZ Output Disable Time 5.0 1.0 6.5 8.5 1.0 9.0 ns tPLZ OE to On tOSLH Output to Output Skew 5.0 0.5 1.0 1.0 ns tOSHL CP to On (Note 8) VCC TA = + 25°CTA = − 40°C to + 85°C Symbol Parameter (V) CL = 50 pF CL = 50 pF Units (Note 9) Typ Guaranteed Minimum tS Setup Time, HIGH or LOW 5.0 3.0 3.0 ns Dn to CP tH Hold Time, HIGH or LOW 5.0 1.5 1.5 ns Dn to CP tH CP Pulse Width 5.0 4.5 5.5 ns HIGH or LOW Symbol Parameter Typ Units Conditions CIN Input Capacitance 4.5 pF VCC = OPEN CPD Power Dissipation Capacitance 55.0 pF VCC = 5.0V |
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