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AM29DL16XDT70EIN Scheda tecnica(PDF) 4 Page - Advanced Micro Devices

Il numero della parte AM29DL16XDT70EIN
Spiegazioni elettronici  16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
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Produttore elettronici  AMD [Advanced Micro Devices]
Homepage  http://www.amd.com
Logo AMD - Advanced Micro Devices

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Am29DL16xD
21533E5 December 1, 2006
D A TA
SH EET
GENERAL DESCRIPTION
The Am29DL16xD family consists of 16 megabit, 3.0
volt-only flash memory devices, organized as 1,048,576
words of 16 bits each or 2,097,152 bytes of 8 bits each.
Word mode data appears on DQ0–DQ15; byte mode
data appears on DQ0–DQ7. The device is designed to
be programmed in-system with the standard 3.0 volt
V
CC supply, and can also be programmed in standard
EPROM programmers.
The device is available with an access time of 70, 90,
or 120 ns. The devices are offered in 48-pin TSOP,
48-ball Fine-pitch BGA, 48-ball Very Thin Profile
Fine-pitch BGA, and 64-ball Fortified BGA packages.
Standard control pins—chip enable (CE#), write enable
(WE#), and output enable (OE#)—control normal read
and write operations, and avoid bus contention issues.
The device requires only a single 3.0 volt power sup-
ply for both read and write functions. Inter nally
generated and regulated voltages are provided for the
program and erase operations.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides si-
multaneous operation by dividing the memory space
into two banks. The device can improve overall system
performance by allowing a host system to program or
erase in one bank, then immediately and simulta-
neously read from the other bank, with zero latency.
This releases the system from waiting for the comple-
tion of program or erase operations.
The Am29DL16xD devices uses multiple bank archi-
tectures to provide flexibility for different applications.
Four devices are available with these bank sizes:
Am29DL16xD Features
The Secured Silicon Sector is an extra sector capa-
ble of being permanently locked by AMD or customers.
The Secured Silicon Sector Indicator Bit (DQ7) is
permanently set to a 1 if the part is factory locked,
and set to a 0 if customer lockable. This way, cus-
tomer lockable parts can never be used to replace a
factory locked part. Current version of device has 64
Kbytes; future versions will have only 256 bytes.
This should be considered during system design.
Factory locked parts provide several options. The Se-
cured Silicon Sector may store a secure, random 16
byte ESN (Electronic Serial Number), customer code
(programmed through AMD’s ExpressFlash service),
or both. Customer Lockable parts may utilize the Se-
cured Silicon Sector as bonus space, reading and
writing like any other flash sector, or may permanently
lock their own code there.
DMS (Data Management Software) allows systems to
easily take advantage of the advanced architecture of
the simultaneous read/write product line by allowing re-
moval of EEPROM devices. DMS will also allow the
system software to be simplified, as it will perform all
functions necessary to modify data in file structures, as
opposed to single-byte modifications. To write or up-
date a particular piece of data (a phone number or
configuration data, for example), the user only needs to
state which piece of data is to be updated, and where
the updated data is located in the system. This is an
advantage compared to systems where user-written
software must keep track of the old data location, sta-
tus, logical to physical translation of the data onto the
Flash memory device (or memory devices), and more.
Using DMS, user-written software does not need to in-
terface with the Flash memory directly. Instead, the
user's software accesses the Flash memory by calling
one of only six functions. AMD provides this software to
simplify system design and software integration efforts.
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard. Commands are written to the command reg-
ister using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or
erase operation is complete by using the device status
bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2
(toggle bits). After a program or erase cycle has been
completed, the device automatically returns to reading
array data.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
V
CC detector that automatically inhibits write operations
during power transitions. The hardware sector pro-
tection feature disables both program and erase
operations in any combination of the sectors of mem-
or y. This can be achi ev ed in-system or via
programming equipment.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the
standby mode. Power consumption is greatly re-
duced in both modes.
Device
Bank 1
Bank 2
DL161
0.5 Mb
15.5 Mb
DL162
2 Mb
14 Mb
DL163
4 Mb
12 Mb
DL164
8 Mb
8 Mb


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