CA3304AD datasheet(5/12 Pages) INTERSIL

Il numero della parte	CA3304AD

Spiegazioni elettronici	4-Bit, 25 MSPS, Flash A/D Converters

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Produttore elettronici	INTERSIL [Intersil Corporation]

Homepage	http://www.intersil.com/cda/home

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5

Functional Diagram

Timing Diagrams

FIGURE 1. TIMING DIAGRAM

FIGURE 2. OUTPUT ENABLE/DISABLE TIMING

†Cascaded Auto Balance (CAB)

NOTE: CE1 and CE2 inputs and data outputs have standard CMOS protection networks to VDD and VSS. Analog inputs and clock have

standard CMOS protection networks to VAA+ and VAA-.

9

7

1

DQ

CLK

DQ

CLK

DQ

CLK

DQ

CLK

DQ

CLK

DQ

CLK

5

2

3

4

6

ENCODER

LOGIC

ARRAY

D

LATCH

16

Q

COUNT

16

COUNT

8

D

LATCH

8

Q

D

LATCH

0

Q

COUNT

1

8

14

VAA-VSS

†CAB COMPARATOR #1

φ1 (AUTO BALANCE)

φ2 (SAMPLE UNKNOWN)

50k

Ω

CLOCK

15

13

VREF-

VREF+

VIN

12

11

16

10

VAA+VDD

φ1

φ2

1/

2R

1/

2R

R

†CAB #8

†CAB #16

OUTPUT

REGISTER

THREE-STATE

DRIVERS

DATA

CHANGE

OVERFLOW

BIT 4

BIT 3

BIT 2

BIT 1 (LSB)

CE1

CE2

R

CLOCK

B1 - B4, DC & OF

COMPARATOR DATA

DATA VALID 2

φ 1

φ 2

tHO

1

0

AUTO

BALANCE

AUTO

BALANCE

AUTO

BALANCE

SAMPLE 1

SAMPLE 2

SAMPLE 3

LATCHED

DATA SHIFTED INTO

OUTPUT REGISTERS

DATA VALID 1

DATA VALID 0

tD

BITS 1-4

DC, OF

tDIS

HIGH

CE2

CE1

IMPEDANCE

HIGH

IMPEDANCE

HIGH

IMPEDANCE

tEN

tDIS

CA3304, CA3304A

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