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MC33023DWR2 Scheda tecnica(PDF) 10 Page - ON Semiconductor

Il numero della parte MC33023DWR2
Spiegazioni elettronici  High Speed Single?묮nded PWM Controller
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Produttore elettronici  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC33023DWR2 Scheda tecnica(HTML) 10 Page - ON Semiconductor

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MC34023, MC33023
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10
In certain applications, it may be desirable to disable the
current limit comparator. This can be accomplished by
biasing pin 11 to a level greater than 1.4 V but less than 3.0 V.
Under these conditions, the shutdown comparator and
soft−start latch are activated during an overcurrent event
causing the converter to enter an hiccup mode.
Undervoltage Lockout
There are two undervoltage lockout circuits within the IC.
The first senses VCC and the second Vref. During power−up,
VCC must exceed 9.2 V and Vref must exceed 4.2 V before
the outputs can be enabled and the Soft−Start latch released.
If VCC falls below 8.4 V or Vref falls below 3.6 V, the outputs
are disabled and the Soft−Start latch is activated. When the
UVLO is active, the part is in a low current standby mode
allowing the IC to have an off−line bootstrap startup circuit.
Typical startup current is 500
mA.
Output
The MC34023 has a high current totem pole output
specifically designed for direct drive of power MOSFETs.
It is capable of up to
± 2.0 A peak drive current with a typical
rise and fall time of 30 ns driving a 1.0 nF load.
Separate pins for VC and Power Ground are provided.
With proper implementation, a significant reduction of
switching transient noise imposed on the control circuitry is
possible. The separate VC supply input also allows the
designer added flexibility in tailoring the drive voltage
independent of VCC.
Reference
A 5.1 V bandgap reference is pinned out and is trimmed
to an initial accuracy of
±1.0% at 25°C. This reference has
short circuit protection and can source in excess of 10 mA
for powering additional control system circuitry.
Design Considerations
Do not attempt to construct the converter on
wire−wrap or plug−in prototype boards. With high
frequency, high power, switching power supplies it is
imperative to have separate current loops for the signal paths
and for the power paths. The printed circuit layout should
contain a ground plane with low current signal and high
current switch and output grounds returning on separate
paths back to the input filter capacitor. Shown in Figure 36
is a printed circuit layout of the application circuit. Note how
the power and ground traces are run. All bypass capacitors
and snubbers should be connected as close as possible to the
specific part in question. The PC board lead lengths must be
less than 0.5 inches for effective bypassing for snubbing.
Instabilities
In current mode control, an instability can be encountered
at any given duty cycle. The instability is caused by the
current feedback loop. It has been shown that the instability
is caused by a double pole at half the switching frequency.
If an external ramp (Se) is added to the on−time ramp (Sn)
of the current−sense waveform, stability can be achieved.
One must be careful not to add too much ramp
compensation. If too much is added the system will start to
perform like a voltage mode regulator. All benefits of
current mode control will be lost. Figure 26 is an example of
one way in which external ramp compensation can be
implemented.
1.25 V
Figure 21. Ramp Compensation
Current
Signal Sn
Ramp Compensation
Ramp Input
Ramp
Compensation Se
A simple equation can be used to calculate the amount of
external ramp slope necessary to add that will achieve
stability in the current loop. For the following equations, the
calculated values for the application circuit in Figure 35 are
also shown.
Se
+
VO
L
NS
NP
(RS)Ai
where:
= DC output voltage
= number of power transformer primary
= or secondary turns
= gain of the current sense network
= (see Figures 24 and 25)
= output inductor
= current sense resistance
VO
NP, NS
Ai
L
RS
= 0.115 V/ms
For the application circuit: Se +
5
1.8
μ
2
8
(0.3)(0.55)


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