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MC100LVEL90 Scheda tecnica(PDF) 2 Page - ON Semiconductor |
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MC100LVEL90 Scheda tecnica(HTML) 2 Page - ON Semiconductor |
2 / 6 page MC100LVEL90 http://onsemi.com 2 D2 D1 Figure 1. Logic Diagram and Pinout: 20-Lead SOIC (Top View) D1 17 18 16 15 14 13 12 4 3 5678 9 Q0 11 10 Q1 Q1 Q2 Q2 VCC D0 19 20 2 1 VCC Q0 D0 D2 VCC VEE GND GND ECL LVPECL ECL LVPECL ECL LVPECL Table 1. PIN DESCRIPTION FUNCTION ECL Inputs LVPECL Outputs ECL Reference Voltage Output Positive Supply Negative Supply Ground PIN Dn, Dn Qn, Qn ECL VBB VCC VEE GND Warning: All VCC, VEE, and GND pins must be externally connected to Power Supply to guarantee proper operation. * All VCC pins are tied together on the die. Table 2. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Power Supply GND = 0 V 8 to 0 V VEE NECL Power Supply GND = 0 V −8 to 0 V VI NECL Mode Input Voltage GND = 0 V VI w VEE −6 to 0 V Iout Output Current Continuous Surge 50 100 mA mA IBB ECL VBB Sink/Source ± 0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm 20 SOIC 20 SOIC 90 60 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board 20 SOIC 30 to 35 °C/W Tsol Wave Solder 265 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. |
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