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MC100LVEL30DWG Scheda tecnica(PDF) 2 Page - ON Semiconductor |
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MC100LVEL30DWG Scheda tecnica(HTML) 2 Page - ON Semiconductor |
2 / 6 page MC100LVEL30 http://onsemi.com 2 D1 Figure 1. Logic Diagram and Pinout: 20-Lead SOIC (Top View) R0 R1 D2 17 18 16 15 14 13 12 4 3 5678 9 Q0 11 10 VCC Q1 Q1 VCC Q2 Q2 VEE D0 19 20 2 1 VCC Q0 CLK0 CLK1 S012 CLK2 R2 D R S Q Q D R S Q Q D R S Q Q Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. R L L H L H Table 1. TRUTH TABLE S L L L H H D L H X X X CLK Z Z X X X Q L H L H Undef Z = LOW to HIGH Transition X = Don’t Care Q H L H L Undef Table 2. PIN DESCRIPTION FUNCTION ECL Data Inputs ECL Reset Inputs ECL Clock Inputs ECL Common Set Input ECL Differential Data Outputs Positive Supply Negative Supply PIN D0−D2 R0−R2 CLK0−CLK2 S012 Q0−Q2; Q0−Q2 VCC VEE Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Mode Power Supply VEE = 0 V 8 to 0 V VEE NECL Mode Power Supply VCC = 0 V −8 to 0 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V VI VCC VI VEE 6 to 0 −6 to 0 V V Iout Output Current Continuous Surge 50 100 mA mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SOIC−20 SOIC−20 90 60 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board SOIC−20 30 to 35 °C/W Tsol Wave Solder <2 to 3 sec @ 248°C 265 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. |
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